Kabushiki Kaisha Toshiba

Toshikazu Sei

Yasunobu Umemoto

Yasunori Tanaka

Muneaki Maeno

Kenji Kimura

Hiroaki Suzuki

Toshiki Morimoto

Yukinori Uchino

Shinsuke Sakamoto

Masakazu Yaginuma

Chihiro Ishii

Katsuro Doke

Eiji Ban

Nobuo Fudanuki

Yasuo Inbe

Kazunari Horikawa

Hiroyuki Hara

Akira Yamaguchi

Shinji Fujii

Youichi Satou

Yoshiaki Hashiba

Teruo Kobayashi

Shinji Ochi

Tomohiro Fujisaki

Kaoruko Yamada

A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Semiconductor integrated circuit with a logic circuit including a data holding circuit

A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal

The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.

Semiconductor integrated circuit with mixed gate array and standard cell

A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Semiconductor integrated circuit device having an ESD protection unit

Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Semiconductor integrated circuit device and wiring arranging method thereof

A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.

Semiconductor integrated circuit device with I/O cell and connection member

A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.

Semiconductor device provided using wiring data of common design core

A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Semiconductor integrated circuit making use of standard cells

Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program

The present invention provides a standard cell which can reduce an effective cell size and improve an integration degree of a semiconductor integrated circuit. The standard cell includes a plurality of MOS transistors formed on a semiconductor substrate. Then, a plurality of standard cells are adjacent to each other in upper, lower, left and right directions, and constitute the semiconductor integrated circuit. The present invention is intended to reduce the effective cell size in such a way that a source region of a MOS transistor connected to a power supply voltage or a ground voltage is shared between cells adjacent to each other. Also, even if the source region is not shared, a source region of one cell in the cells adjacent to each other is arranged in an empty space region of the other cell in such a way that it bestrides between the cells adjacent to each other.

Standard cell having a special region and semiconductor integrated circuit containing the standard cells

A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

Growing community of inventors

Kawasaki, Japan

Toshikazu Sei