Nec Electronics Corporation

Renesas Electronics Corporation

Nsk Corporation

Toshikazu Murata

Kouichi Nishimura

Atsushi Shimatani

Yasutomo Shikanai

Hiromichi Ohtsuka

In order to attach cup bearingswith good precision in portions between circular holesthat are formed in joining-arm sectionsof yokesof a cross shaft universal jointand the tip-end sections of a shaft sectionof a cross shaftregardless of variation in the dimensions of the joining-arm sections, the circular holesin the tip-end sections thereof, and the cup bearings, and elastic deformation of the joining-arm sectionsof the yokeduring press-fitting work, press-fitting punchesare used to pressure fit the cup bearingsto a preset reference position inside the circular holes, and the value of the pressure that is applied to the press-fitting punches at that instant is set as a reference pressure, and at the instant when the pressure applied to the press-fitting punches becomes larger than the reference pressure by a preset specified value, the cup bearingsare determined to have reached positions where press-fitting is complete.

Assembly method for cross shaft universal joint

An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.

Output circuit

A differential amplifier circuit includes: an NMOS transistor pair connected with a non-inversion input terminal and an inversion input terminal; a PMOS transistor pair connected with the non-inversion input terminal and the inversion input terminal; and an output circuit section. The PMOS transistor pair includes first and second PMOS transistors, and the NMOS transistor pair includes first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well. The output circuit section includes a first current mirror of a folded cascode type connected with the first and second non-doped type NMOS transistors, and outputs an output voltage in response to a current from the first current mirror.

Differential amplifier circuit, data line driver using the same, and liquid crystal display apparatus

Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.

Differential amplifier and display device using the same

A differential signal receiver according to the present invention includes a waveform shaping circuit selectively outputting an upper limit value having a first potential difference from a first power supply potential, and a lower limit value having a second potential difference from the upper limit value, from a first and a second output terminals according to a differential signal input, and an amplifier comparing voltages of the first and the second output terminals and outputting one of a voltage almost the same as the first power supply potential or a voltage almost the same as a second power supply potential.

Differential signal receiver

A gradation voltage selecting circuit includes a plurality of gradation selecting MOS Tr groups, M-pieces half gradation voltage MOS Tr groups, a switching portion and a control portion. Each of the plurality of gradation selecting MOS Tr groups corresponds to one gradation voltage. The M-pieces half gradation voltage MOS Tr groups are connected to each other in series. The control portion supplies a second signal in response to a second display data. The first gradation selecting MOS Tr group selects a first gradation voltage in response to the second signals. The second gradation selecting MOS Tr group selects a second gradation voltage in response to the second signals. The first and second gradation selecting MOS Tr groups and the M-pieces half gradation voltage MOS Tr groups voltage-divide a gradation voltage between the first gradation voltage and the second gradation voltage into (M+2) equal parts in response to the second signal, and generate (M+1)-pieces half gradation voltages. The switching portion selects and outputs one of the (M+1)-pieces half gradation voltages into the display portion in response to the second signal. The (M+1)-pieces half gradation voltages are determined by ON resistance of the first and second gradation selecting MOS Tr groups and the half gradation voltage MOS Tr group.

Growing community of inventors

Kanagawa, Japan

Toshikazu Murata