Mitsubishi Denki Kabushiki Kaisha

Toshikazu Masumoto

Shinobu Takahama

Hisatoshi Arita

The present invention implements an armoring case of a power semiconductor device which can prevent cracks from occurring by inserting the terminal portion of an electrode plate in the inserting hole of the armoring case and then bending the same, misregistration from occurring between the fastening bolt inserting hole of the terminal portion and the screw portion of a terminal nut, and the like, and which can easily be assembled automatically. A terminal nut cover is previously molded. The terminal nut cover includes a first concave portion which can cover and support the terminal nut so as not to rotate when fastening a bolt, and a second concave portion into which the tip of the screw portion of the bolt can project. The electrode plate whose terminal portion is previously bent into a predetermined shape by a press machine or the like, and the terminal nut cover having the terminal nut inserted in and supported by the first concave portion are provided in a metal mold for the armoring case. The electrode plate and the terminal nut cover are insert-molded integrally with the armoring case, so that the armoring case of the power semiconductor device can be molded.

Power semiconductor device, armoring case thereof and method for

Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.

Method of fabricating power semiconductor device and lead frame

In order to maintain parasitic inductances of main electrodes at low levels also during operation of a semiconductor device, upright portions of main electrode plates serving as paths of main currents are sealed in a side wall portion of a resin case, whereby the main electrode plates are fixed to the case while being maintained in parallel with each other. Further, lower end portions are opposed in parallel with each other through a flat insulating spacer. Thus, parasitic inductances caused in the main electrode plates are suppressed. Further, the lower end portions are not fixed to a circuit board but electrically connected to a power transistor through wires. Therefore, no deformation of the main electrodes is brought by thermal deformation of the circuit board following heat generation of the transistor, whereby the parallelism of the main electrode plates is maintained also during the operation of the device. Consequently, the parasitic inductances are maintained at low levels also during operation of the device.

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Tokyo, Japan

Toshikazu Masumoto