Texas Instruments Corporation

Hitachi, Ltd.

Other

Toshikazu Kumai

Yoshitaka Tadaki

Toshihiro Sekiguchi

Keizo Kawakita

Toshiyuki Kaeriyama

Michio Tanaka

Songsu Cho

Katsuo Yuhara

Michio Nishimura

Hideo Aoki

Jun Murata

Kazuhiko Saitoh

Shinya Nishio

Kazuhiko Saito

Takeshi Sakai

Takafumi Tokunaga

Kiyomi Katsuyama

Yuji Ezaki

Minoru Ohtsuka

Akihiko Konno

Masayuki Yasuda

Takashi Hayakawa

Takatoshi Kakizaki

Yoshimi Torii

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Method of forming a semiconductor device have a screen stacked cell

A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Method of manufacturing a semiconductor integrated circuit device using

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Dallas, TX, United States of America

Toshikazu Kumai