Kabushiki Kaisha Toshiba

Toshikazu Kawamura

Motohiko Okabe

Jun Takehara

Naruhiko Aramaki

Masayuki Murakami

Hiroshi Nakatani

Yoshito Sameda

Yukitaka Yoshida

Yoichi Takayanagi

When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint () that receives a memory read request transmitted by the root complex, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex () returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

PCI.Express communication system and communication method thereof

A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line

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Tokyo, Japan

Toshikazu Kawamura