Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Toshikazu Hirai

Tetsuro Asano

Mikito Sakakibara

Tetsuro Sawai

Toshikazu Imaoka

Hisanori Uda

Koichi Hirata

Yasoo Harada

Takayoshi Higashino

Masao Nishida

Tsutomu Aono

Osamu Isaki

Hitoshi Tsuchiya

Keiichi Honda

With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n-type region&#x2014;insulating region&#x2014;second n-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second nregions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Method of forming a protecting element comprising a first high concentration impurity region separated by an insulating region of a substrate

With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n-type region-insulating region-second n-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second nregions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Protecting element having first and second high concentration impurity regions separated by insulating region

A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.

Semiconductor device

A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. The gate width of each FET is about 400 &#x3bc;m, and the maximum power required for the device operation is maintained by a lager conductivity of the channel layer of one FET and by a lower conductivity of the channel layer of another FET. The device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Semiconductor switching device

Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN&#x2014;first control terminal Ctl-, between the common input terminal IN&#x2014;second control terminal Ctl-, between the first control terminal Ctl-&#x2014;the first output terminal OUT, and between the second control terminal Ctl-&#x2014;the second output terminal OUT, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad Oor O. The electrostatic energies that are applied between the first output terminal OUT&#x2014;the first control terminal Ctl-, between the common input terminal IN&#x2014;the first control terminal Ctl-, between the second output terminal OUT&#x2014;the second control terminal Ctl-, and between the common input terminal IN&#x2014;the second control terminal Ctl-can be respectively attenuated to the same degree and most efficiently.

Switching circuit device

A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &#x3bc;m and a signal receiving FET has a gate width of 400 &#x3bc;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

In a case of a semiconductor chip having an electrode pad to be wire-bonded to a header, securing of a fixing region is difficult since the spread of an Ag paste cannot be controlled, therefore, there has existed a problem such that stable manufacturing could not be carried out. Also, there existed a problem such that realization of stable manufacturing resulted in an excessively large external package form. A projection part is provided in a header, and a fixing region of a bonding wire is secured by arranging a chip at a position shifted in a direction to become distant from the projection part. An electrode pad to be connected to the header is arranged closer to the chip center than the other electrode pads of the identical chip side, and a wire is extended therefrom to the projection part or in the vicinity thereof so as to cross the chip and is fixed. Thereby, downsizing of the package and stable manufacturing are realized.

A switching device receives two pairs of balanced signals and outputs one of the two pairs of the signals. The device is composed of two SPDT switches which share two control signals provided to the gates of the FET of the SPDT switches. The package of the device has eight external electrodes on the back side of the package. The eight external electrodes are configured so that they are aligned symmetrically with respect to the center line of the package. The device requires only a small package space and is suitable for mobile communication application such as cell phone accommodating CDMA and GPS signals.

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &#x3bc;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &#x3bc;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &#x3bc;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device

A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs.

A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device with depletion layer stop region

A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.

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Ora-gun, Japan

Toshikazu Hirai