Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Toshikatsu Jinbo

Kazuo Watanabe

Hiroyuki Takahashi

Hiroyuki Kobatake

Hiroshi Furuta

Noriaki Kodama

Atsunori Hirobe

Muneaki Matsushige

Naoaki Sudo

Tetsuo Fukushi

Atsunori Miki

Hironori Nakamura

Teiichiro Nishizaka

Koji Naganawa

Takaki Kohno

Kiyokazu Hashimoto

Hiroshi Sugawara

Hidetaka Natsume

Kiyokazu Ishige

Kenji Hibino

Noriyuki Ohta

Kazuhisa Ninomiya

Takayuki Kurokawa

Hiroyasu Kitajima

Kenichi Ushikoshi

A semiconductor storage deviceaccording to an aspect includes a first memory areaand a second memory area. Memory cells MC_m_n and bit lines BL, BL_, . . . , BLmare disposed in a boundary areabetween the first and second memory areasand. The memory cells MC_m_n disposed in the boundary areaincludes memory cells into which no data is written, and a lineis formed in a place that overlaps memory cells disposed in the boundary areawhen the boundary areais viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Semiconductor storage device

A semiconductor storage deviceaccording to an aspect includes a first memory areaand a second memory area. Memory cells MC_m_n and bit lines BL, BL_, . . . . , BLm_are disposed in a boundary areabetween the first and second memory areasand. The memory cells MC_m_n disposed in the boundary areaincludes memory cells into which no data is written, and a lineis formed in a place that overlaps memory cells disposed in the boundary areawhen the boundary areais viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Semiconductor device

A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Voltage reducing circuit

Semiconductor device and control method thereof

Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage. The startup non-operating step-down circuit group includes the multiple step-down circuits sequentially selected from one having a shortest wiring distance from the power-on reset circuit.

Semiconductor device and method of supplying internal power to semiconductor device

A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.

A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Semiconductor integrated circuit device and dummy pattern arrangement method

A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.

Pulse generating circuit and semiconductor device provided with same

A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.

Non-volatile semiconductor storage device having a salicide structure

A non-volatile flash memory ( ) that may have an improved layout freedom is disclosed. Non-volatile flash memory ( ) may include banks (B and B ). Each bank (B and B ) may include memory cell arrays (MCA to MCA ) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y S and Y S ). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y S and Y S ) and a bank switch group (Y S and Y S ). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Non-volatile semiconductor memory

Disclosed is a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming, to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations.

Semiconductor memory device and write/readout controlling method error correction code decoding device

According to the present invention, a voltage of 10.5 V, a voltage of 6.5 V and a voltage of 0.5 V are respectively applied to the control gate, the drain and the source of a memory cell that is a programming target. And a voltage of 0 V (a ground voltage) is applied to the control gate of a memory cell that is not a programming target and that does not belong to the row in which of the programming target memory cell is located. As a result, it is ensured that the memory cell that is not the programming target is non-conductive, and that the drain-substrate electrical field of the memory cell that is the programming target is reduced.

Growing community of inventors

Tokyo, Japan

Toshikatsu Jinbo