Fuji Electric Co., Ltd.

Toshihito Kamei

Seiji Noguchi

Souichi Yoshida

When forming a p+ area and n+ area on the same surface of an n&#x2212; semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n&#x2212; semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n&#x2212; semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n&#x2212; semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n&#x2212; semiconductor wafer than the p+ type area. Thereafter, the n&#x2212; semiconductor wafer is exposed to an oxygen (O) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n&#x2212; semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.

Method of manufacturing semiconductor device

IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an ntype semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and ntype drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a ptype spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.

Growing community of inventors

Saitama, Japan

Toshihito Kamei