Sony Semiconductor Solutions Corporation

Sony Corporation

Toshihiro Yamaguchi

Hiroshi Shono

Satoshi Okada

Yuichi Hirayama

Koichi Ohya

Shinichi Kitazono

The present technology relates to a tuner IC capable of reducing the cost of a demodulation LSI. A tuner includes an IF output terminal configured to output an IF signal of terrestrial broadcasting, a first output terminal configured to output the IF signal or one of BB signals that are output signals of satellite digital broadcasting and have orthogonal phases, and a second output terminal configured to output another of the BB signals. The present technology can be applied to a broadcast receiving system.

Tuner IC

The present technology relates to a semiconductor chip and a receiving apparatus capable of suppressing increases in size and cost due to circuit complexity. A tuner includes an RF input terminal to which an RF signal of terrestrial broadcasting is input, a first-IF input terminal to which a first-IF signal of satellite digital broadcasting is input, a first filter that filters a signal in a frequency band lower than a predetermined frequency, a second filter that filters a signal in a frequency band equal to or higher than the predetermined frequency, and a switch that causes the RF signal to be input to the first filter or to the second filter by switching according to a frequency of the RF signal, and causes the first-IF signal to be input to the first filter or to the second filter by switching according to a frequency of the first-IF signal. The present technology may be applied to a broadcast receiving system.

Semiconductor chip and receiving apparatus

A signal processing device includes an interface, which includes a demodulation processing unit that executes demodulation processing, a processing unit that executes demux processing or the like, and a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the processing unit, that transmits data signals as two-bit parallel transmission.

Signal processing device and signal processing method

The invention provides a television reception circuit wherein a front end circuit of a television receiver is integrated and outputting of an image frequency is suppressed. The television signal reception circuit comprises an integrated circuit which in turn includes an automatic gain circuit for controlling a level of an input signal, first and second frequency mixture circuits to which an output of the automatic gain circuit is inputted, a &pgr;/2 phase shifting circuit for supplying local oscillation frequencies having a phase difference of &pgr;/2 from each other to the first and second frequency mixture circuits, first and second &pgr;/4 phase shifting circuits for shifting phases of outputs of the first and second frequency mixture circuits by &plus;&pgr;/4 and &minus;&pgr;/4, respectively, and an addition circuit for adding outputs of the first and second &pgr;/4 phase shifting circuits. The television signal reception circuit outputting a television signal inputted to the integrated circuit through a variable frequency tuning circuit as an intermediate frequency signal. Also an automatic phase shift control circuit and an equal amplitude addition circuit suitable for use with a television signal reception circuit are disclosed.

Growing community of inventors

Kanagawa, Japan

Toshihiro Yamaguchi