Ricoh Company, Ltd.

Nec Corporation

Toshihiro Tsukagoshi

Toshiyuki Furuta

Hirotoshi Eguchi

Hiroyuki Horiguchi

Yutaka Ebi

Yoshio Watanabe

Tatsuya Furukawa

Keiichi Iwasaki

Takahiro Watanabe

Tomonori Tanaka

Noriyuki Terao

Junichi Ikeda

Sugitaka Oteki

Hiroo Kitagawa

Hidetake Tanaka

Iwao Hamaguchi

Koji Oshikiri

Naoki Tsumura

Satoru Numakura

Hiroyuki Kimbara

Shuji Motomura

Satoshi Otsuki

Yutaka Maita

Atsuo Hashimoto

Atsuhiro Oizumi

Eiki Aono

Takashi Kitaguchi

Mitsutaka Iwasaki

Keiichi Yoshioka

Masanobu Fukushima

Takashi Yasui

Tomohiro Mizutani

Masashi Tokuda

Katsuhiro Tobita

Yasuo Ueda

Takatsugu Maeda

Michihito Ootsuki

Masazumi Sukekawa

There is provided a head driving device for causing a head to discharge droplets. The device includes a drive circuit, a first drive waveform generation circuit, a second drive waveform generation circuit, and a correction circuit. The drive circuit is configured to drive the head based on a plurality of drive waveforms to discharge the droplets. The first drive waveform generation circuit configured to generate a first drive waveform of the plurality of drive waveforms. The second drive waveform generation circuit is configured to generate a second drive waveform of the plurality of drive waveforms. The correction circuit is configured to correct the first drive waveform and the second drive waveform with reference to an intermediate potential.

Head driving device and image forming apparatus including same

A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Dead-time generating circuit and motor control apparatus

A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.

PLL control circuit

An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Information processor configured to detect available space in a storage in another information processor

A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

High speed serial switch fabric performing mapping of traffic classes onto virtual channels

A VRAM stores a plurality of patterns of image data, an offset register stores values which indicate definition starting positions from which display image data are defined from the plurality of patterns of image data, respectively, a horizontal counter counts dots in a horizontal scanning direction, and a vertical counter counts lines in vertical scanning direction. Address and control signals are successively provided for reading a respective line of the display image data from the VRAM within one horizontal scanning period, based on the values of the offset register and the value of the vertical counter. Each of two second storage devices has a storage capacity for storing a thus-read respective line of the image data. Thus-read image data is written at addresses of a predetermined one of the two second storage devices, the addresses corresponding to displaying dots of the image data, while, according to the value of the horizontal counter, image data stored in the other one of the two second storage devices is read out, where, the image data writing and reading operations are performed alternately between the two second storage devices for each horizontal scanning period.

Image display control device, method and computer program product

A neuron unit processes a plurality of input signals and outputs an output signal which is indicative of a result of the processing. The neuron unit includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part.

Neuron unit, neural network and signal processing method

A hierarchical signal processing apparatus includes aggregates having logic operation portions. The apparatus compares a final output signal from a logic operation portion in a final aggregate with a teaching signal, and generates an error signal by taking a signal which exists only in the teaching signal as a positive error signal, and taking a signal which exists only in said final output signal as a negative error signal. An error signal generating portion in the apparatus generates a positive error signal of a logic operating portion within a certain aggregate which supplies one or more output signals thereof to said logic operation means of another aggregate based on one or more logic operations on the excitatory weight function signal of said weight function signal, the positive error signal, the inhibitory weight function signal of said weight function signal and the negative error signal, and also generates a negative error signal of said logic operation means within said certain aggregate which supplies one or more output signals thereof to said logic operation means of said other aggregate based on one or more logic operations on the inhibitory weight function signal of said weight function signal, the positive error signal of said other aggregate, the excitatory weight function signal of said weight function signal and the negative error signal.

Signal processing apparatus including plural aggregates

A neuron unit processes a plurality of input signals and outputs an output signal which is indicative of a result of the processing. The neuron unit includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a generating part for generating new weight functions based on an error signal representing an error between the output signal of the forward process part and a teaching signal and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The error signal includes first and second error signal components representing pulse densities.

Neuron unit with error signal having components representing pulse

A neuron unit processes a plurality of input signals and for outputs an output signal which is indicative of a result of the processing, and includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a function generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The supplying part includes a memory for storing each weight function in the form of a binary value, and a generating circuit for generating a random pulse train based on each binary value stored in the memory. The random pulse train describes each weight function in the form of a pulse signal having a pulse density.

Neuron unit

A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r&gt;q, and each weighting coefficient is described by a pulse density.

Neuron unit and neuron unit network

A knowledge inferential processing apparatus comprises an external interface section for inputting and outputting information between the knowledge inferential processing apparatus and the exterior thereof; a rule base memory for representing knowledge as a combination of a plurality of rules constructing a premise conditional section and a conclusive section as a pair, and storing the represented knowledge; a rule pointer table for storing a rule pointer group indicative of a sequence for applying the rules within the rule base memory; an inferential processing section for interpreting and executing the rules and judging whether or not the matching is formed with respect to the respective rules; a memory section for storing fact data sent to the inferential processing section and conclusive data generated during the inferential processing; an inferential hysteresis recording section for recording a rule pointer of the matched rule in the matched sequence with respect to the inferential processing results executed by the inferential processing section; and a control section for sequentially sending the rules to the inferential processing section in accordance with the rule pointer group and sending the rule pointer of the matched rule to the inferential hysteresis recording section with respect to the inferential processing results executed by the inferential processing section.

Knowledge inferential processing apparatus

A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.

Gate array device having a memory cell/interconnection region

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Itami, Japan

Toshihiro Tsukagoshi