Ricoh Company, Ltd.

Toshihiro Takahashi

Yasutaka Tsukamoto

Naohiko Nishigaki

Toshiya Murota

A sufficient and necessary number of operation cycles for detecting faults, which have not been found by a function test, are accurately and rapidly selected by performing a logical simulation of an operation of an integrated circuit including m internal nets. A fault simulation is performed by using a predetermined test pattern so as to specify internal nets for which a fault is detected. Standby cycles are detected from among operation cycles in the logical simulation. .alpha. internal nets at which a fault is detected by the fault simulation from among the m internal nets to be subjected to the IDDQ test are excluded. The standby cycles are selected as the IDDQ test cycles based on the (m-.alpha.) internal nets.

Method for selecting operation cycles of a semiconductor IC for

Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values '0' and '1' to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.

It is determined whether a given logic state surely fulfills a predetermined logic-state condition, and also it is also determined whether the given logic state possibly fulfills the predetermined logic-state condition. The determination by the first determining unit is performed by determining whether the given logic state is a certain state and also agrees with a logic state required by the predetermined logic-state condition. The determination by the second determining unit is performed by determining whether the given logic state is an uncertain state and therefore does not completely agree with the logic state required by the predetermined logic-state condition. The predetermined logic-state condition is predetermined so that, when a signal having a logic state required by the predetermined logic-state condition appears at a relevant pin of a given electric circuit, no legal DC current flows through the relevant pin.

Test-vector editing system and method

Logical simulation result data is obtained from performing a logical simulation operation on a logical circuit to be tested. The logical simulation result data is then examined and thus a test point is obtained for a DC parametric test in which direct-current characteristics of the logical circuit are tested. The logical simulation result data indicates input logical signal levels applied to input terminals and output logical signal levels appearing at output terminals in response to application of the input logical signal levels to the input terminals, and further indicates how the input logical signal levels and output logical signal levels vary as time progresses. It is determined whether or not a desired logical signal level is held at a predetermined circuit terminal of the input terminals and output terminals for a predetermined level maintenance time period in the logical simulation result data.

System and method for automatically determining test point for DC

A DC test point finding method includes steps of: displaying a list of all input and output terminals of an integrated circuit; inputting selected terminals among the terminals of the list; inputting a selected test pattern file among a number of stored test pattern files, each test pattern file including a plurality of sequentially occurred test vectors and identified by a name of the test pattern file, the test vectors identified by respective vector numbers; inputting a test point finding condition related to a DC test point; finding the DC test point of the circuit among the selected terminals by using the test vectors of the selected test pattern file and the test point finding condition; and inserting test point data of the DC test point into the list so that the resulting list including the test point data is displayed.

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Osaka, Japan

Toshihiro Takahashi