Matsushita Electric Industrial Co., Ltd.

Nippon Hoso' Kyokai

Panasonic Corporation

Nippon Hoso Kyokai, Both of

Toshihiro Miyoshi

Yuichi Ninomiya

Naoji Okumura

Yoshimichi Ohtsuka

Toshiro Ohmura

Hisaji Murata

Hideyuki Ikuhara

Tadashi Kawashima

Takushi Iwamoto

Manabu Yumine

Toshiyuki Fukuda

Masahiro Kawashima

Toshiaki Tsuji

Fumito Itou

Minoru Miyata

Toshiya Noritake

Tetsuo Kutsuki

Kenji Ishikawa

Kunihiko Fujii

Kazuyasu Yamamoto

Keisuke Kodera

Hisashi Arita

Naoki Kurita

Kazuhide Fujimoto

An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip protrudes more along a normal to the first surface than ends of the external terminals do.

Electronic component module and an assembly including the same

The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Vertical synchronizing signal generation apparatus and video signal processing apparatus

A DD converter circuit for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit for writing a digital video signal which is output by the DD converter circuit on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Sampling frequency converter, sampling frequency conversion method, video signal processor, and video signal processing method

An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided. The analog-to-digital converter according to the invention comprises an A-D converter circuit for converting an analog television signal to a 2 -bit digital signal, a synchronizing signal detecting circuit for detecting a synchronizing signal from the digital signal received from the A-D converter circuit, a Y/C separating circuit for separating a luminance signal and a carrier chrominance signal from the digital signal from the A-D converter circuit using the synchronizing signal from the synchronizing signal detecting circuit, a synchronizing signal converter circuit for converting a synchronizing signal portion of the luminance signal into a predetermined value, and a digital amplifying circuit for digitally amplifying the signal level from the synchronizing signal converter by a predetermined multiple value specified by a standard for communication or for video signal apparatus. The digital amplifying circuit may be composed of a shifter. A low pass filter may be used additionally to eliminate rounding errors. Further, depending on the type of video signal, the low pass filter may be bypassed.

Video signal level converting device and video signal analog-to-digital converter

A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.

Television receiver for receiving multi-standards

A digital audio signal demodulation circuit comprises a synchronous detection circuit (18) and a muting circuit (17) for muting the output from an interpolation circuit (16) using a synchronization lock signal generated from the synchronous detection circuit (18) when synchronization has been lost. The differential signal output from the interpolation circuit (16) is muted by the muting circuit (17) and thereafter integrated by an integration circuit (19). Thus, an audio signal with high sound quality can be demodulated without producing interruption noise even when synchronization has been lost or forcible muting is done.

Audio signal demodulation circuit

Video signal switching circuit especially suitable for high definition

Interframe deinterleave switching circuit

An apparatus for receiving and selecting high-definition television signals and NTSC standard television signals includes a high-definition display screen device having an aspect ratio of 16 to 9. The NTSC standard television signals have an aspect ratio which is different than the 16 to 9 aspect ratio of the high-definition display screen device. A first signal converter is for converting the NTSC standard television signals into first quasi-high-definition television signals identifying a first displayed image corresponding in vertical length to a vertical length of the high-definition display screen device. A second signal converter is for converting the NTSC standard television signals into second quasi-high-definition television signals identifying a second displayed image corresponding in horizontal length to a horizontal length of the high-definition display screen device. Switching circuits are provided for selecting one of the high-definition television signals and the first and second quasi-high-definition television signals.

Apparatus for receiving and selecting high-definition television (HDTV)

Growing community of inventors

Osaka, Japan

Toshihiro Miyoshi