Matsushita Electric Industrial Co., Ltd.

Toshihiro Kohgami

Katsuya Arai

Shiro Usami

Hiroaki Yabu

An inventive semiconductor integrated circuit device includes: an external connection terminal; an electrostatic discharge protection circuit; an output circuit; an output prebuffer circuit; an input prebuffer circuit; an internal circuit; an inter-power supply electrostatic discharge protection circuit; and a gate voltage control circuit. The gate voltage control circuithas a capacitorand a resistor, and the inter-power supply electrostatic discharge protection circuithas an NMIS transistor. When a positive surge is applied to the external connection terminal, the gate potential of the NMIS transistoris also increased. Thus, the NMIS transistoris turned on, and the positive electrical charge supplied to the external connection terminalis discharged toward a ground line

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit and an internal circuit, and is configured so that the output circuit is protected by the electrostatic discharge protection circuit from a surge entering through the external connection pad. A substrate-potential-fixing PMIS transistor whose gate is connected to the external connection pad is provided between an n-type substrate region (n well) and a power supply line. When a positive charge is applied to the external connection pad in an ESD test, the substrate-potential-fixing PMIS transistor is turned OFF, thereby suppressing an increase in the potential of the power supply line and suppressing a decrease in the surge withstand voltage of the output circuit.

A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit, an output-signal-fixing circuit and an internal circuit. The output-signal-fixing circuit includes a first capacitor and a second capacitor and fixes an output signal from a second pre-buffer circuit at an &ldquo;L&rdquo; level (low voltage) even when an output from the internal circuit is in a floating state. During an ESD test, since an output signal from the second pre-buffer circuit is fixed at an &ldquo;L&rdquo; level (low voltage) by the output-signal-fixing circuit, the NMIS transistor is in an OFF state. In this manner, a surge current is prevented from flowing locally into the NMIS transistor.

Semiconductor integrated circuit device including an ESD protection circuit with an improved ESD protection capability for input or output circuit protection

Growing community of inventors

Kyoto, Japan

Toshihiro Kohgami