National Institute Of Advanced Industrial Science And Technology

Other

Duaxes Corporation

Bits Co., Ltd.

Toshihiro Katashita

Kenji Toda

Yohei Hori

Mitsugu Nagoya

Kazumi Sakamaki

Hiroyuki Ota

Shinichi Ouchi

Tetsuji Yasuda

Meishoku Masahara

Yongxun Liu

Kazukuni Kobara

Hanpei Koike

Kazuhiko Endo

Tatsuro Maeda

Koichi Fukuda

Takeshi Inui

Yasunori Terashima

Yasuhiro Ogasahara

Osamu Morikawa

Tadamasa Takayama

Toshihiro Matsui

Toshifumi Irisawa

Akashi Satoh

A semiconductor deviceof the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits, andhaving a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Semiconductor device including circuit having security function

A method and a program capable of controlling an error rate of device-specific information are provided. Provided is the method for controlling an error rate of device-specific information, including a step Sof: inputting each of i (i is an arbitrary natural number) challenges, j times (j is an arbitrary natural number), into a PUF mounted chip; leaving j responses intact (j'=j) or processing j responses into j&#x2032; pieces (0&#x3c;j&#x2032;&#x3c;j); and registering them in the database beforehand in association with each piece of the input data, a step Sof inputting i challenges into the database, a step Sof: reading j&#x2032; responses corresponding to the respective i challenges from the database; concatenating the j&#x2032; responses for each piece of the input data; further concatenating the concatenated data by k&#x2032; repetitions (0&#x3c;k&#x2032;&#x2264;k, and k is an arbitrary natural number, but is a natural number of 2 or more if the i and the j are both 1); obtaining the concatenated (j&#x2032;&#xd7;k&#x2032;) responses for each piece of the input data; and further concatenating them also for different input data to obtain concatenated (i&#xd7;j&#x2032;&#xd7;k&#x2032;) responses and thereby generate reference data, a step Sof: inputting i challenges, k times, for each challenge into the PUF mounted chip; leaving obtained k responses intact as k&#x2032;=k or processing the obtained k responses into k&#x2032; pieces (0&#x3c;k&#x2032;&#x3c;k); concatenating obtained k&#x2032; responses by j&#x2032; repetitions for each response; further concatenating them for all of the k&#x2032; responses; further concatenating concatenated (j&#x2032;&#xd7;k&#x2032;) responses also for different input data; and obtaining concatenated (i&#xd7;j&#x2032;&#xd7;k&#x2032;) responses to generate synthesized output data, and a step Sof deciding whether or not the synthesized output data matches the reference data (specifically, whether a Hamming distance between both data is a threshold value or less), and the method determines whether or not the error rate of the synthesized output data is within a preset range based on the decision result in step S, and changes at least one of i, j, j&#x2032;, k, and k&#x2032; to repeat steps Sto Suntil the error rate falls within the preset range if the error rate is determined not to be within the preset range.

Method for controlling error rate of device-specific information and program for controlling error rate of device-specific information

This invention provides an electronic circuit component authenticity determination method capable of determining whether an electronic circuit component is a component manufactured by an authorized manufacturer. The electronic circuit component is operated under a predetermined condition at the time of manufacturing or initialization of the electronic circuit component. The waveform of power consumption or an electromagnetic wave at the time of the operation is measured and stored as first waveform data. An authenticity determination target electronic circuit component is operated under the predetermined condition. The waveform of power consumption or an electromagnetic wave is measured and temporarily stored as second waveform data. The stored first waveform data is compared with the second waveform data. It is determined that the electronic circuit component is a genuine when the waveform data match. It is determined that the electronic circuit component is a counterfeit product when the waveform data are different.

Electronic circuit component authenticity determination method

Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

FPGA-based network device testing equipment for high load testing

An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

Image display apparatus

A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2bits. For example, when m2bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2bits, a CRC circuit that processes every m2bits, . . . , and a CRC circuit that processes every m2bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Cyclic redundancy checking value calculator

Growing community of inventors

Tsukuba, Japan

Toshihiro Katashita