Renesas Electronics Corporation

J-Devices Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

J-Device Corporation

Toshihiro Iwasaki

Shinji Baba

Michitaka Kimura

Shinji Watanabe

Hiroaki Matsubara

Tomoshige Chikai

Kiminori Ishido

Michiaki Tamakawa

Masaki Watanabe

Yasumichi Hatanaka

Keiichiro Wakamiya

Kozo Harada

Hirokazu Honda

Shingo Nakamura

Sumikazu Hosoyamada

Yoshikazu Kumagaya

Shotaro Sakumoto

Takeshi Miyakoshi

Takashi Nakamura

Satoshi Yamada

Kazuyuki Nakagawa

Muneharu Tokunaga

Hiroshi Demachi

Yoshikazu Shimote

Masatoshi Yasunaga

Naoki Hayashi

Shiori Idaka

Takeumi Kato

Takanori Okita

Koichiro Niwa

A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

Semiconductor device and method for manufacturing same

This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Semiconductor device

The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, fluxis applied to the solder bumpsfor flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumpsand make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.

Semiconductor device and manufacturing method therefor

An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect structure

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer,) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrateand a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

Semiconductor device and manufacturing method thereof

Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.

Semiconductor package and manufacturing method thereof

A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Semiconductor package

A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate; a first insulating material layerformed on the support plate; a non-volatile magnetic memory elementfixed on the first insulating material layer; a second insulating material layerthat encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer, a soft magnetic layerorand a conductive portionconnecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield partcontaining a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Magnetic shielding package of non-volatile magnetic memory element

A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Manufacturing method for semiconductor device

A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Heat sink in the aperture of substrate

To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

Method of manufacturing semiconductor device and semiconductor device

Growing community of inventors

Tokyo, Japan

Toshihiro Iwasaki