Sanyo Electric Co., Ltd.

Toshihiro Itagaki

Sadao Yoshikawa

An address transition detector (ATD) for a memory device detects a change in an address signal and in response, produces a timing signal. The timing signal is used to align the timing of operation of a memory cell and a sense amp with the timing of the change in the address signal. The ATD includes a detection circuit for detecting a change in the address signal and a transistor having its gate connected to an output of the detection circuit, its source connected to ground and its drain connected to a first input terminal of a logic gate. An output of the logic gate is connected to an inverter. The output of the inverter is connected to a node between the transistor and the first input terminal of the logic gate. The output of the logic gate is also connected to a pair of series connected delay circuits. The output of the second delay circuit is input to a second input terminal of the logic gate. The first delay circuit delays the rising edge of the signal output from the logic gate and the second delay circuit delays the falling edge of the signal output from the logic gate.

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Gifu-ken, Japan

Toshihiro Itagaki