Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toshihiro Ishikawa

Katsuhiko Ueda

Hidetoshi Suzuki

Minoru Okamoto

Mikio Sakakihara

Mitsuru Uesugi

Ryuji Fuchikami

Yukihiro Fujimoto

Takayuki Sasaki

Nobuo Asano

Ryutaro Yamanaka

Toshio Sugimura

Noriaki Minamida

Mikako Yasutome

Takashi Nishitoba

An electronic apparatus () comprises processors ()-(), devices ()-(), and a peak power-managing unit (). The peak power-managing unit () includes a power information storage unit () operable to store a total power consumption value, and a suspended request storage unit () operable to store suspended use requests. Each of the processors ()-() addresses, to the peak power-managing unit (), a use request for the use of a target device among the devices ()-(). The peak power-managing unit () issues a device use permit notification to the processor when determining that the operation of the target device still maintains an added total power consumption value within a specified value. Upon receipt of the device use permit notification, the processor sets up a course of action to be provided by the target device. As a result, controlled peak power is provided, and the devices can be run according to updated information.

Electronic apparatus and peak power-controlling method related thereto

Digital signal processing sectionhas reconfigurable device, and reconfigurable deviceconfigures decoding sectionand coding sectionby programming data. Decoding sectionacquires synchronization from a signal output from reception section, and demodulates and decodes the signal. CPUdownloads programming data of another radio communication system to store in storage sectionvia general bus. Further, CPUreads out the stored programming data, and reconfigures reconfigurable device. Storage sectionstores the programming data.

Communication apparatus and method for reconfiguring communication apparatus

Shift register stores data read from data memory through data bus, and supplies a shift output to shift register. Shift register stores operation target data read from data memory through data bus, shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit. Bit selection circuit selects bit data, which is placed at a position designated by register, from data stored in shift register. Multi-input exclusive OR circuit executes exclusive OR operations of all bits of bit data output from bit selection circuit, simultaneously, and outputs an operation result of one bit to shift register. This makes it possible to efficiently perform convolutional code processing at high speed.

Operation processing apparatus and operation processing method

Shift register stores data read from data memory through data bus , and supplies a shift output to shift register . Shift register stores operation target data read from data memory through data bus , shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit . Bit selection circuit selects bit data, which is placed at a position designated by register , from data stored in shift register . Multi-input exclusive OR circuit executes exclusive OR operations of all bits of bit data output from bit selection circuit , simultaneously, and outputs an operation result of one bit to shift register . This makes it possible to efficiently perform convolutional code processing at high speed.

An arithmetic apparatus comprising a memory 1 for storing path select signals, a barrel shifter 3 for shifting data read from the memory, a shift register 4 for receiving a bit shifted to a MSB by the barrel shifter and means 5 for generating the number of shifts which are performed by the barrel shifter by converting data positioned at a specific bit position in the shift register, wherein path select signals at the same time are divided into a plurality of groups, and then stored in the memory, and the arithmetic apparatus includes address generating means 10 for outputting the address, and address conversion means 7 for generating the address of the group which must be read by combining the address and a value of a specific bit position in the shift register with each other. Thus, tracing back in Viterbi decoding can be performed with a short bit width.

Arithmetic apparatus for use in Viterbi decoding

An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inputted to a shift register to thereby perform Viterbi decoding at a high speed.

Arithmetic apparatus for carrying out viterbi decoding at a high speed

A fixed-point arithmetic unit has a calculation controller for detecting number of significant bits of data to be calculated and controlling an adder so as to inhibit it from transferring a carry to a portion of the adder unnecessary for calculation of the significant bits and a register controller for controlling a register adapted to store input and output of the adder such that only the significant bits of data are stored in the register, whereby when the significant bits of data is smaller than a bit width of the arithmetic circuit, consumptive power of the arithmetic unit can be reduced.

Fixed-point arithmetic unit

The present invention discloses a pipeline processor system comprising a pipeline processor and a memory device, wherein the memory device is comprised of a memory unit for holding data and/or an instruction as well as being accessed to implement memory read operation or memory write operation in a clock cycle; and a data latch unit for latching data to be written into the memory unit, while the pipeline processor is comprised of an instruction detection unit for detecting from fetched instructions a first predetermined instruction which directs the latch of the data as well as a second predetermined instruction which directs write of the data at the data latch means into the memory means; and a latch control unit for controlling to latch operation results of the first predetermined instruction to the data latch unit when the predetermined instruction is detected by the instruction detection unit as well as controlling to write the data at the data latch unit into the memory unit when the second predetermined instruction is detected. The first predetermined instruction includes operand fetch from the memory unit replaced with the latch of the operand, the operand fetch encompassing two memory accesses having been planned in a clock cycle together with the memory write operation; and the second predetermined instruction includes execution of an instruction and the write of the data at the data latch means into the memory means, the instruction placing after the first predetermined instruction and excluding its own memory access.

Pipeline processor which avoids resource conflicts

An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

Interleaved memory wherein plural memory means comprising plural banks

An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.

Arithmetic unit for executing division

An arithmetic apparatus includes an arithmetic logic unit for performing a given arithmetic operation of double precision data having a preselected number of bits, a first register storing results of the arithmetic operation of higher-order bits in the double precision data, a second register storing results of the arithmetic operation of lower-order bits in the double precision data, an overflow-detection circuit for detecting overflow conditions of the results of the arithmetic operations, a maximum/minimum value-setting circuit for setting the results of the arithmetic operation to be stored in the first register to one of maximum and minimum values according to the overflow conditions, and a correction circuit for correcting an output value indicative of he results of the arithmetic operation provided by the second register to one of a first value defined by a bit sequence of 0s and a second value defined by a bit sequence of 1s according to the overflow condition.

Arithmetic apparatus with overflow correction means

In a digital signal processor, an arithmetic apparatus capable of performing Viterbi decoding processing at a high speed with minimum addition of hardware and least overhead of memory. Pathmetric value and branchmetric value read out from first and second memories on two paths are simultaneously added by an adder at most significant bits and least significant bits thereof. A comparator compares values of the most significant bits and the least significant bits output from the adder to generate a path select signal indicating the value which is pathmetrically smaller. The select signal is stored in a shift register on a bit-by-bit basis. Of the values of the most significant bits and the least significant bits of a register storing the output of the adder, the smaller one as decided by the path select signal is written in the memory at eight most significant bits or least significant bits thereof via distributor, a bus and a register.

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Yokohama, Japan

Toshihiro Ishikawa