Ricoh Company, Ltd.

Toshihiro Hyodo

Takeshi Hino

A semiconductor manufacturing process simulation apparatus using a diffusion model in which a dislocation loop generated in a crystalline substrate during an ion implantation process of a semiconductor manufacturing process is considered with respect to a diffusion in a heat treatment process subsequent to the ion implantation process. An ion implantation process simulating part simulates an ion implantation process. A model generating part generates a diffusion model in which contribution of dislocation loops is considered, the dislocation loops being formed in the substrate during the ion implantation process. A heat treatment process simulating part simulates a heat treatment process subsequent to the ion implantation process, the diffusion model generated by the model generating part being used for simulating diffusion of impurities in the substrate during the heat treatment process. A pressure field generated by the dislocation loops in the substrate is defined in the diffusion model by a function of a distance from a layer in which the dislocation loops are formed.

Semiconductor manufacturing process simulation apparatus for calculating

A process simulation apparatus simulates a manufacturing process of a semiconductor device which manufacturing process comprising various processes including an ion implantation process and a diffusion process. Process sequence data which represents conditions of a two-dimensional simulation for each process is input to a memory unit. The memory unit stores the process sequence data and also stores condition information for various simulation models usable for each process. An optimum simulation model for each process is selected for performing a two-dimensional simulation for each process. The semiconductor device manufacturing process is simulated by a two-dimensional simulation method using the selected optimum simulation model.

Process simulation apparatus and method for selecting an optimum

The present invention relates to a semiconductor memory device having a planner cell structure. A source with a large area is formed on a P-type silicon substrate, a plurality of strip-like word lines are formed in parallel to each other on the source, gate oxide films are formed on both side walls of each of the word lines, and an epitaxial layer is formed between the word lines. A plurality of strip-like bit lines are formed in parallel to each other perpendicularly to the word lines on the oxide film, and the epitaxial layer, and a drain is formed in the epitaxial layer under a polycrystalline silicon film of the bit line. A channel is formed in contact with the gate oxide film between the drain and the source in the epitaxial layer, and an electric current flows in a longitudinal direction when a memory element becomes ON.

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Ikeda, Japan

Toshihiro Hyodo