Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hatachi Ltd

Hitachi, Ind.

Toshihiko Takakura

Akihisa Uchida

Yoichi Tamaki

Masao Kawamura

Katsumi Ogiue

Daisuke Okada

Kazuhiko Sagara

Makoto Yoshida

Takeo Shiba

Shigeo Kuroda

Mikinori Kawaji

Katsuyuki Asaka

Nobuhiko Ohno

Shinji Nakashima

Norio Hasegawa

Hirotaka Nishizawa

Shinji Okazaki

Daisuke Okaka

A plurality of first contact holes reaching an n -type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n -type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n -type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n -type semiconductor area used as the drain through the second contact holes.

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor integrated circuit device and process for manufacture of the same

A plurality of first contact holes reaching an n,-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n,-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n,-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n,-type semiconductor area used as the drain through the second contact holes.

A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Method of manufacturing semiconductor device with constant width deep

A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

Process of manufacturing semiconductor integrated circuit device having

Method of fabricating a semiconductor substrate, and semiconductor

Process of manufacturing semiconductor integrated circuit device and

A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Growing community of inventors

Koganei, Japan

Toshihiko Takakura