Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Other

Hitachi Europe Limited

Toshihiko Sato

Takahiro Naito

Yoshiyuki Kado

Takafumi Kikuchi

Hikaru Ikegami

Ryoichi Nakatani

Hiroshi Kikuchi

Nobuyuki Inaba

Toshikazu Shimada

Haroon Ahmed

Hideko Ando

Kiyoo Itoh

Tetsuya Hayashida

Kazuo Nakazato

Ikuo Yoshida

Hiroshi Mizuta

Shinji Yuasa

Satoshi Imasu

Masakazu Ichikawa

Kazuyuki Taguchi

Norio Kishikawa

Tomo Shimizu

Of three chips (A), (B), and (C) mounted on a main surface of a package substrate () in a multi-chip module (MCM), a chip (A) with a DRAM formed thereon and a chip (B) with a flash memory formed thereon are electrically connected to wiring lines () of the package substrate () through Au bumps (), and a gap formed between main surfaces (lower surfaces) of the chips (A), (B) and a main surface of the package substrate () is filled with an under-fill resin (). A chip (C) with a high-speed microprocessor formed thereon is mounted over the two chips (A) and (B) and is electrically connected to bonding pads () of the package substrate () through Au wires ().

Semiconductor device and manufacturing method thereof

Method of manufacturing semiconductor device

A memory device includes a memory node ( ) to which charge is written through a tunnel barrier configuration ( ) from a control electrode ( ). The stored charge effects the conductivity of a source/drain path ( ) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers ( ) of polysilicon of 3 nm thickness and layers ( ) of Si N of 1 nm thickness, overlying polycrystalline layer of silicon ( ) which forms the memory node. Alternative barrier configurations ( ) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands ( ), which act as the memory node, distributed in an electrically insulating matrix.

Memory device

There is proposed a high-sensitive TMR element wherein the selection of electronic state contributing to tunnel conduction is optimized. In this invention, a junction plane between a ferromagnetic layer ( ) having a bcc structure and a tunnel barrier layer ( ) is constituted by ( ) plane or ( ) plane of the ferromagnetic layer ( ). The tunnel barrier layer ( ) is formed of a thin aluminum oxide film which is formed through two stages, i.e. a first stage wherein an aluminum film having a thickness of 1 nm or less is formed on the surface of a magnetic metal by taking advantage of the excellent wettability of aluminum to the surface of metallic film, the resultant aluminum film being subsequently naturally oxidized or oxidized by oxygen radical; and a second stage wherein an aluminum thin film is formed directly from an aluminum flux in an oxygen atmosphere or an atmosphere of oxygen radical.

Tunneling magnetoresistive head and a process of tunneling magnetoresistive head

A magnetic sensor is constructed to be capable of detecting the change of tunnel current due to co-tunneling effect at a high S/N ratio by using a tunneling magneto-resistive element having a first magnetic layer of a soft magnetic material formed on a flat substrate, first and second tunnel barrier layers formed on the first magnetic layer, magnetic particles of a ferromagnetic material provided between the first and second tunnel barrier layers, and a second magnetic layer of a soft magnetic material formed on the second tunnel barrier layer so as to create tunneling junctions.

Magnetic device

An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.

Electronic device and a method of manufacturing the same

A central portion of a main face of a package substrate is mounted with a memory chip using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers are mounted at vicinities of the memory chip . A clearance between a main face (lower face) of the memory chip and a main face of the package substrate is filled with underfill resin (seal resin) constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin is extended to an outer side of the memory chip and covers entire faces of the chip condensers mounted at vicinities of the memory chip

Semiconductor device and a method of manufacturing the same

Magnetic head

Growing community of inventors

Kodaira, Japan

Toshihiko Sato