Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Toshihiko Nakauchi

Masato Hirai

Shigeki Morimoto

Norikazu Endo

Masami Kurata

A method of compensating a phase of a system clock for use in a system clock circuit for receiving an external clock to produce a system clock for an information processing system, in which the quantity of phase variation of the external clock supplied from a reference clock oscillator provided outside the system is detected; in accordance with the detected quantity of phase variation, the phase variation of the external clock supplied from the reference clock generator is compensated to supply the compensated external clock to the system clock circuit; whether or not a state of the external clock supplied from the reference clock oscillator provided outside the system is abnormal is detected; and in accordance with the detected state of the external clock, one of the external clock supplied from the reference clock oscillator and the compensated external clock is selected to supply the selected external clock to the system clock.

Method of compensating a phase of a system clock in an information

A method and apparatus for controlling the phase of a system clock, in which one of a first clock signal and a second clock signal is selected and output to a system as a system clock signal, the first clock signal being generated by a frequency synthesizer synchronized with an external clock signal supplied from a reference clock signal oscillator provided externally of the system, and the second clock signal being supplied from another reference clock signal oscillator provided internally of the system, and the phases of the first and second clock signals are controlled, prior to switching between the first and second clock signals and supplying the switched clock signal to the system as the system clock signal. The switching is delayed for a period while there is a phase shift between the first and second clock signal , when the system clock signal is switched between the first and second clock signal.

Method and apparatus for controlling phase of a system clock signal for

A method is provided for controlling bus-using rights in a multi-bus system which has a plurality of buses and a plurality of units connected to each of the buses. A unit connected to one bus is accessible by another unit connected to another bus. When a first unit accesses either a second unit on the one bus or a third unit on another bus, two requests for use of the one and another buses are issued substantially at the same time, thereby reducing the time taken for acquiring a bus-using right of the another bus. As soon as it is found that access is directed to the second unit on the one bus, the request for using the another bus is canceled, thus reducing a bus occupation rate for the another bus.

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Hadano, Japan

Toshihiko Nakauchi