Fujitsu Corporation

Agency of Industrial Science and Technology

Fujitsu Microelectronics Limited

Photonics Electronics Technology Research Association

Toshihiko Mori

Yasufumi Sakai

Yuuki Ogata

Masafumi Kondou

Motomu Takatsu

Naoki Yokoyama

Yoshiaki Nakata

Yoshiki Sakuma

Shinsuke Tanaka

Shoichiro Kawashima

Miyoshi Saito

Tatsuya Usuki

Hiroshi Nakao

Toshiro Futatsugi

Yasumoto Tomita

Kenichi Imamura

Makoto Hamaminato

Masafumi Kondo

A frequency characteristic adjustment circuit is disclosed. The frequency characteristic adjustment circuit is disposed between an optical circuit element and a drive circuit for driving the optical circuit element. A capacitor is connected to an output of the drive circuit. A current supply circuit is controlled by a voltage generated by the drive circuit. The current supply circuit supplies a different current value depending on a voltage received from the drive circuit to the optical circuit element.

Frequency characteristic adjustment circuit, optical transmission module using the same, and optical transceiver

There is provided a driver circuit including a variable current-source configured to include, a first current-source coupled to a first input node to which a first signal is input from an external, a second current-source coupled to a second input node to which a second signal as an inversion of the first signal is input from the external, a first bypass circuit coupled between the first current-source and the first input node, the first bypass circuit being switched according to the second signal, and a second bypass circuit coupled between the second current-source and the second input node, the second bypass circuit being switched according to the first signal, and a terminal circuit configured to be terminated for an optical device driven by a drive signal according to the first signal, the drive signal being output from an output node coupled between the terminal circuit and the variable current-source.

Driver circuit, optical transmission module and optical transmission device

Disclosed is a frequency characteristic adjusting circuit disposed between an optical circuit element and a drive circuit driving the optical circuit element. The frequency characteristic adjusting circuit includes a capacitor, and two or more series circuits having a resistor and a switch, the two or more series circuits being connected in parallel with the capacitor, where resistance with respect to the switch that is turned on is changed according to an output voltage of the drive circuit by changing ON or OFF of the switch such that electric charge at a contact point between the optical circuit element and the capacitor is adjusted to be constant regardless of the output voltage of the drive circuit.

Frequency characteristic adjusting circuit, optical transmitter, and optical transceiver

An optical transmitter includes: a driving circuit that includes drivers each corresponding to a configuration bit of an input electrical data sequence; a MZ optical modulator that includes a first phase shifter provided in an arm and a second phase shifter provided in an arm; first capacitance elements that are electrically connected between the driving unit and the first phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a first multilevel signal to be supplied to the first phase shifter; and second capacitance elements that are electrically connected between the driving circuit and the second phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a second multilevel signal to be supplied to the second phase shifter.

Optical transmitter, optical modulator module, and optical transmission system

A decision feedback equalizer for N-level amplitude modulated signal, includes: (N&#x2212;1) level conversion circuits to add (N&#x2212;1) shifting voltages to the amplitude modulated signal respectively; (N&#x2212;1)&#xd7;N determination feedback equalization-correction circuits to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of a reception data ahead of one data cycle, on each of the (N&#x2212;1) level shifted signals to generate (N&#x2212;1) sets of N equalization correction signals; (N&#x2212;1)&#xd7;N comparison circuits; (N&#x2212;1)&#xd7;N first latch circuits; (N&#x2212;1) selection circuits to select a comparison result of the N comparison circuits in each (N&#x2212;1) sets; (N&#x2212;1) second latch circuits; and a decoder, wherein each of the (N&#x2212;1) selection circuits selects an equalization-correction signal among the N equalization-correction signals in each (N&#x2212;1) set according to outputs latched by the (N&#x2212;1) second latch circuits.

Decision feedback equalizer

A phase interpolator has: a mixer configured to synthesize phases of a plurality of input cosine-wave or sine-wave signals whose phases are different from each other; and a bias generator configured to output a bias signal in accordance with a phase control signal to the mixer, and the mixer outputs a signal with a phase in accordance with the phase control signal.

Phase interpolator

A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Clock control circuit, receiver, and communication device

A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

DC-DC converter and semiconductor integrated circuit

A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.

PLL frequency synthesizer

A variance correction method includes generating a reference current depending on a resistance within a lowpass filter and outputting the reference current to a voltage controlled oscillator, and correcting characteristics of the lowpass filter and a gain of the voltage controlled oscillator based on an output clock of the voltage controlled oscillator.

Variance correction method, PLL circuit and semiconductor integrated circuit

A level converter includes a cross-coupled section for holding data and a first switching section connected in series with the cross-coupled section and supplied with a differential input signal. The level converter has a second switching section, a current mirror connection section, a third switching section, and an input/output matching evaluation section. The second switching section is connected in parallel with the cross-coupled section, and the current mirror connection section is connected in a current-mirror configuration with a transistor in the second switching section. The third switching section is connected in series with the current mirror connection section, and the input/output matching evaluation section is used to control a transistor in the third switching section by receiving the input signal and an output node signal.

Level converter

A level down converter having a first inverter supplied a first power supply voltage, and outputting signals made by logical inversions of input signals, and a second inverter supplied a second power supply voltage being lower than the first power supply voltage, and outputting signals made by logical inversions of output signals from the first inverter, is provided. The first inverter contains a transistor including a gate insulation film having a first film thickness. The second inverter contains a transistor including a gate insulation film having a second film thickness which is thinner than the first film thickness.

Level down converter

A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line. The second transistor has a current input terminal connected to the power source line and a current output terminal connected to the second bit line. A transistor drive circuit drives, during a write recovery period, one of the first transistor and the second transistor which is connected to one of the first bit line and the second bit line which is set to a lower potential.

Semiconductor memory device and a semiconductor integrated circuit

A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions. Technologies of manufacturing a semiconductor element on a semiconductor substrate capable of reducing the number of fine pattern fabrication processes by photolithography or capable of dispensing with these processes.

Semiconductor integrated circuit using monolayer epitaxial growth

A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

Growing community of inventors

Isehara, Japan

Toshihiko Mori