Hitachi, Ltd.

Toshihiko Kurihara

Hiromitsu Imori

Kenji Matsubara

Takashi Hotta

Shigeya Tanaka

Kotaro Shimamura

Hideo Sawamoto

Koji Saito

Akiyoshi Osumi

A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Data processor having cache memory

An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching

An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical level caches connected to the processing unit and the main memory as arranged so that a primary cache close to the processing unit is a first level cache, and a secondary cache close to the main memory is a second level cache. The prefetch instruction, when executed, causes the processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the two hierarchical level data caches, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

An information processing system including a processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Information processing system with prefetch instructions having indicator bits specifying a quantity of operand data for prefetching

A processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Processing device which prefetches instructions having indicator bits specifying cache levels for prefetching

An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching

Data processor with variable types of cache memories and a controller for selecting a cache memory to be access

An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Growing community of inventors

Hadano, Japan

Toshihiko Kurihara