International Business Machines Corporation

Toshihiko Kurihara

Hung Qui Le

Alexander Erik Mericas

Robert Dominick Mirabella

Masahiro Tokoro

Michitaka Okuno

Hideki Mitsubayashi

A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.

Method for measuring memory latency in a hierarchical memory system

A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

Analyzing instruction completion delays in a processor

A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.

Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters

A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.

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Kanagawa-ken, Japan

Toshihiko Kurihara