Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Toshihiko Kitazume

Shinya Takeda

Nobuhiro Tsuji

Shunsuke Kodera

Yoshio Furuyama

Tetsuya Iwata

Kenichirou Kada

Hirosuke Narai

Yukio Ishikawa

Teruyuki Matsuoka

Fuying Yang

Atsushi Shiraishi

Mikio Takasugi

Tsuyoshi Ukyo

Tsuyoshi Ukyou

A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.

Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit

A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.

Memory device that communicates error correction results to a host

A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.

Memory system having a semiconductor memory device with protected blocks

A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.

Memory device that updates parameters transmitted to a host based on operational settings

A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.

Memory system including test circuit

A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.

Memory system

A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.

Memory system that handles access to bad blocks

A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.

Memory device that performs an advance reading operation

According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than '2', by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1&#x3c;=s&#x3c;t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being '1', when the number of error bits exceeds the predetermined value s.

Error correction device and error correction method

According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.

Error detecting device and memory system

A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chipand chip, each of the chips composed of a large number of memory cells capable of storing two-bit data in one memory cell in units of two types of pages, the memory controller including a NAND I/F with the semiconductor memory section, and a CPU configured to execute writing programs repeatedly for two types of pages in a memory cell which belongs to the chipand thereafter execute writing programs into a memory cell which belongs to the chip

Growing community of inventors

Kawasaki Kanagawa, Japan

Toshihiko Kitazume