Kabushiki Kaisha Toshiba

Burr-brown Corporation

Texas Instruments Corporation

Toshihiko Hamasaki

Toshio Murota

Yoshiaki Shinohara

Shigetoshi Nakao

Hitoshi Terasawa

Ei-ichi Arihara

Hideki Satake

Haruki Komano

Tadahiro Takigawa

Kyoji Matsusako

Keiji Matsuki

A method and apparatus for improving an S/N ratio in a digital-to-analog conversion of a PDM signal are provided. A digital-to-analog conversion system comprises an S/N ratio improving section. The S/N ratio improving section has a signal component extractor which extracts a signal component included in the PDM signal, and outputs a digitally filtered output signal. The digitally filtered output signal has a second full scale smaller than a first full scale of the PDM signal. The S/N ratio improving section also comprises a full-scale matching unit which matches the second full scale of the digitally filtered output signal with a third full scale of digital-to-analog conversion.

Method and apparatus for improving S/N ratio in digital-to-analog conversion of pulse density modulated (PDM) signal

A digital-to-analog converter is provided for accomplishing analog output characteristics using different digital-to-analog conversion type digital signal processing schemes. A plurality of bits of a received digital signal are divided into a plurality of bit groups. A digital signal processing unit includes a plurality of bit group digital signal processors for receiving the plurality of bit groups. The plurality of digital signal processors employ one or more digital-to-analog conversion type digital signal processing schemes for generating a plurality of digital signal processed outputs. The converter adds the plurality of digital signal processed outputs to generate a composite signal processed output, and includes a weight generating unit for controlling a plurality of shared weight generating elements in response to the composite digital signal processed output to generate an analog output signal.

Digital-to analog-converting method and digital-to analog converter employing common weight generating elements

A waveform shaping circuit for use in a function circuit is provided which minimizes interference with a feedback circuit of the function circuit and a load. The waveform shaping circuit disposed in the function circuit includes a voltage transfer unit and a voltage-to-current converter unit. The voltage transfer unit transfers a voltage at an output terminal of an operational amplifier to the converter unit in an electrically isolated condition. The converter unit has a predetermined threshold for the magnitude of the voltage at the output terminal. The converter unit supplies an inverting input terminal of the operational amplifier with a current having a magnitude depending on a relationship in magnitude between the voltage at the output terminal and the predetermined threshold. In one embodiment of the invention the waveform shaping circuit is used to prevent the onset of instability in a high order delta sigma modulator.

Waveform shaping circuit for function circuit and high order delta sigma

An integrated circuit resistor array suitable for use as resistors included in a high performance analog integrated circuit is provided. A plurality of resistor stripes are collectively arranged in a region on a substrate. The resistor stripes are made of the same material and designed to have the same cross-sectional area. The resistor stripes are electrically connected through first metal layer conductors. Second metal layer conductors connect the stripes to external circuits. Different resistors have matched voltage dependencies.

Integrated circuit resistor array

A digital-to-analog converter is provided which compensates for relative errors among weighting elements used for D/A conversion. The converter includes a decoder, a rotator, and a weighting section. The rotator receives decoded signals from a decoder to produce rotated output signals for activating or deactivating a plurality of weighting elements, respectively, included in the weighting section. The rotated output signals assure that the same number of weighting elements are activated in each of a plurality of sub-periods of time constituting a main period of time of the D/A conversion and that each of the plurality of weighting elements is activated the same number of times during the whole main period.

Rotation system for correction of weighting element errors in

Differential filters for removing both normal-mode and common-mode noises are provided. A first-order differential low pass filter is composed of a first resistor connected between a first input terminal and a first output terminal, a second resistor having the same resistance value as the first resistor and connected between a second input terminal and a second output terminal, a first capacitor connected between the first output terminal and a reference potential, a second capacitor having the same capacitance value as the first capacitor and connected between the second output terminal and the reference potential, and a third capacitor connected between the first output terminal and the second output terminal.

Differential filter circuit and integrated circuit structure therefor

An inverter device is provided which comprises an inverter including a pair of transistors, and first and second delay circuits. The first and second delay circuits are connected to respective inputs of the pair of transistors so as to cause the transistors of the pair to switch with a greater time difference, thereby reducing noise due to switching operations in the inverter.

Switching control circuitry for low noise CMOS inverter

An oversampling digital-to-analog converter is provided with an auto-muting circuit which reduces noise in an analog output signal when a digital input signal remains at zero. Auto-muting circuit includes an input reference level code detection section which detects an input reference level code in the digital input signal. An output reference level code in a modulated output generated from an oversampling modulator is detected by an output reference level code detection section provided in the auto-muting circuit. A modulated output alteration section is provided which operates in response to the result of the detections to selectively pass the modulated output without any alteration or alter the modulated output by substituting it with output reference level codes.

Oversampling digital-to-analog converter with auto-muting feature

A heterojunction bipolar transistor of this invention is a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer. A method of fabricating the transistor includes the steps of forming a first semiconductor layer of a first conductivity type on a substrate, which first semiconductor layer serves as a collector layer, etching an unnecessary portion of the first semiconductor layer to form a groove, and burying an insulating layer in the groove, forming a second semiconductor layer serving as a base layer on the first semiconductor layer and that part of the insulating layer surrounding the first semiconductor layer, and forming a third semiconductor layer of the first conductivity type, serving as an emitter layer, on the second semiconductor layer. According to the method of this invention, a groove is formed, in advance, in an unnecessary part of the first semiconductor layer, which becomes the collector layer, and the insulating layer is buried in the groove. Thus, a flattened wafer having an element region defined therein can be obtained. The second semiconductor layer which becomes the base layer is formed on the wafer, following which the third semiconductor layer serving as the emitter layer is formed. Thus, the base-collector junction area can be reduced to a minimum necessary value. In addition, the surface with a small stepped portion can be obtained.

Method of fabricating a miniaturized heterojunction bipolar transistor

A bipolar transistor excellent in the high speed performance comprises a buried region of a first conductivity type formed in a semiconductor substrate, said buried region having a high impurity concentration, a collector region of the first conductivity type formed on the buried region, a base region of a second conductivity type formed on the collector region, an emitter region of the first conductivity type formed on the base region, and an outer base region of the second conductivity type formed to surround the base and collector regions in such a manner that an ohmic contact is provided between the base region and said outer base region and a p-n junction is formed between the collector region and said outer base region. The concentration profile of the second conductivity type impurity in the depth direction of the outer base region is controlled in such a manner that, while the maximum voltage is applied between the base and emitter regions to turn the transistor on, the concentration of the second conductivity type impurity in the outer base region is kept higher than the concentration of the second conductivity type carrier in a base-widening region formed within the collector region, when the comparison is made at the same depth.

Bipolar transistor

In a method for manufacturing a heterojunction bipolar transistor using a silicon microcrystal as an emitter, a mask 4 having an opening on an element forming region of the main surface of an n-type silicon monocrystal substrate 1 serving as a collector, a p-type outer base 5 is formed on a part of the element forming region of the main surface of the substrate via the opening of the mask 4 by ion-implanting p-type impurity therein, a p-type inner base 6 is formed on the entire surface of the element forming region of the substrate 1 by ion-implanting p-type impurity therein after removing the mask 4, and an n-type emitter 8 is formed by depositing an n-type silicon microcrystal layer on the inner base 6 at a growth velocity of 15 .ANG./sec by a plasma chemical vapor deposition method in a state that the temperature of said substrate 1 is maintained at a constant temperature between 460.degree. to 550.degree. C.

Method for manufacturing a bipolar semiconductor device

Disclosed is a focusing ion beam apparatus, comprising an ion source, focusing and deflecting means for focusing and deflecting an ion beam obtained by the ion source, and a plurality of gas introducing means for a plurality of gases to be supplied onto the surface of a sample to deposit an insulating film. According to the apparatus, a silicon compound gas and a gas mainly consisting of an element other than silicon as a plurality of the gases are supplied onto the surface of the sample, then the ion beam obtained from the ion source is irradiated onto the gases. Thereby, the gases are decomposed so that an insulating film consisting of a silicon oxide or a silicon nitride is deposited on a desired oxide or a silicon nitride is deposited on a desired position of the surface of the sample.

Method of depositing an insulating film and a focusing ion beam apparatus

A bipolar transistor including an emitter region of a first conductivity type, having a predetermined width, an inner base region of a second conductivity type, formed below the emitter region and contacting the emitter region, thus forming a PN junction, an outer base region of the second conductivity type, having a high impurity concentration, set in ohmic contact with the edge of the inner base region and surrounding the inner base region, an inner collector region of the first conductivity type, formed below the inner base region and contacting the inner base region, thus forming a PN junction, and an outer collector region of the first conductivity type, set in ohmic contact with the inner collector region, contacting the lower surface of the outer base region, thus forming a PN junction, and surrounding the inner collector region. The transistor is characterized in the following respects. First, the inner collector region has a higher impurity concentration than the outer collector region. Second, the edge of the inner collector region is located right below, or inner than, the edge of the emitter region. Third, the upper surface of the inner collector region is higher and closer to the emitter region, than the upper surface of the outer collector region.

A method of manufacturing an ultra-miniaturized bipolar transistor is disclosed, wherein an insulating film and a first polysilicon film doped with an impurity of a second conductivity type are formed, in this order, as a collector on a semiconductor layer of a first conductivity type. After an opening is formed in a predetermined portion of the first polysilicon film, the insulating film is etched, using the first polysilicon film as a mask, to expose part of a surface of the substrate. Thereafter, an undoped second polysilicon film is deposited on the resultant structure, and is annealed without etching. Then, the impurity doped in the first polysilicon film is diffused into part of the second polysilicon film and simultaneously into the substrate to form an external base region of a second conductivity type. The second polysilicon film is etched by use of an etching method wherein the etching rate in an undoped region is much higher than that in an impurity-doped region. As a result, the undoped region can be selectively removed without using a mask, thereby exposing the substrate surface. Subsequently, an oxide film is formed on the polysilicon film and the substrate surface, and an impurity is doped through the opening to form an internal base layer. Thereafter, an emitter layer is formed, in a self-aligned manner, in the internal base region.

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Yokohama, Japan

Toshihiko Hamasaki