Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toshihiko Fukuoka

Taemi Wada

Kazuhiro Ohta

Yoshihiko Fukumoto

Daisuke Hayashi

Takaya Hayashi

Hiroyuki Senda

Shigeru Soga

Tatsuji Ishii

Machiya Kumazawa

A terminal apparatus of a communication system is provided with an MAC section (bidirectional communication apparatus), a PHY section, a tuner, and a back-end section. The MAC section comprises a downstream data processing block having a function of substituting for a portion of the process of the CPU, a upstream data processing block having a function of substituting for a portion of the process of the CPU, a bus data arbitration processing block, a CPU bus, the CPU, and a storage apparatus. The downstream data processing block and the upstream data processing block perform direct data transmission/reception while bypassing the CPU bus.

Bidirectional communication control apparatus, terminal apparatus, and bidirectional communication control method

The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Encryption/decryption device and method, encryption device and method, decryption device and method, and transmission/reception apparatus

An interface block () converts the format of input downstream data (STRM). A CPU () receives the format-converted data (DIF) and realizes the MAC function. A TEK process block () receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Device and method for controlling digital bidirectional communication

A decoding device compares the number of errors estimated from input data syndromes by an error number estimation section with the number of errors computed by an error number computation section during decoding process, performs error correction by an error correction section based on this comparison result and the input data syndromes, performs a syndrome computation for error corrected data by a syndrome computation section again to obtain corrected data syndromes, and outputs input data as second corrected data when erroneous correction is performed or the estimated number of errors differs from the computed number of errors.

Method and device for decoding Reed-Solomon code or extended Reed-Solomon code

In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Device and method for error and sync detection

The present invention provides a Reed-Solomon decoding apparatus comprising a device for monitoring occurrence of an error beyond an error correction capability and a degree of error correction. The Reed-Solomon decoding apparatus of the present invention comprises a Reed-Solomon decoder and a correction state monitor. The correction state monitor detects a process error in a Eucledean algorithm computer and a chain retrieval unit in the Reed-Solomon decoder, and generates a signal indicating the degree of error in input data.

Reed-Solomon decoding apparatus and control method therefor

There are provided a Reed Solomon coding apparatus and a Reed Solomon coding method which are capable of performing a Reed Solomon coding process in a way adapted to case where a primitive polynomial, a generator polynomial, and a number of errors to be corrected are changed. The apparatus comprises a generator polynomial coefficient generation block which receives a primitive polynomial set value and a generator initial value as inputs, expands the generator polynomial to generate coefficient data using these values, and a data coding block which receives the primitive polynomial set value and divides an information polynomial by the generator polynomial using the value , thereby coding data.

Reed Solomon coding apparatus and Reed Solomon coding method

A waveform equalization coefficient generator for generating equalization coefficients for taps of digital filters for equalizing signal waveforms is disclosed which is smaller in circuit size and consumes less electric power in comparison with conventional waveform equalization coefficient generators. In a data selection means in a complex arithmetic unit, a first data selection unit selects between real part data and imaginary part data of an equalization coefficient, a second data selection unit selects between real part data and imaginary part data of a received signal, and a third data selection unit selects between EI (error data in the I-axis direction) and EQ (error data in the Q-axis direction). A sum-of-products means is provided which has one multiplier and one adder. The multiplier carries out an operation of multiplying together the output of the data selection means (the real part data or the imaginary part data, whichever is selected) and the output of the data selection means (the Q-axis direction error data or the I-axis direction error data, whichever is selected). The adder carries out an operation of summing together data which are obtained from results of the multiplying operation. Accordingly, either the real part data or the imaginary part data of the equalization coefficient output from the data selection means is updated.

Apparatus and method for waveform equalization coefficient generation

Integrating AFC/APC function with waveform equalization function for and reducing the circuit size of a signal wave-form equalizer apparatus. A waveform equalization section is divided into an FFE block as an anterior stage and a DFE block as a posterior stage. An AFC/APC block is provided therebetween. In the AFC/APC block, an AFC/APC coefficient update section updates a coefficient used for removing frequency and phase errors in accordance with an LMS algorithm, and a tap multiplies a modulated signal by the updated coefficient. Error data produced by an error estimation block is used by not only FFE and DFE coefficient update sections but also the AFC/APC coefficient update section for updating the coefficients. That is to say, the waveform equalization section and the AFC/APC block use the error estimation block in common, thereby reducing the circuit size considerably.

Signal waveform equalizer apparatus

Reed Solomon error correcting circuit and method and device for Euclidean mutual division

A syndrome calculation unit 101 forming a first pipeline stage, a Euclidean algorithm arithmetic operation/error value calculation unit 102 and a Chien search unit 103 together forming a second pipeline stage, and an error correction unit 105 forming a third pipeline stage are provided. The unit 102 implements, by iterative use of a single inverse element calculator, a single Galois multiplier, and a single Galois adder, the Euclidean algorithm arithmetic operation of finding an error locator polynomial .sigma.(z) and an error evaluator polynomial .omega.(z) from a syndrome polynomial S(z) and the calculation of finding an error value e.sub.u by dividing an error evaluation value .omega.(.alpha..sup.-ju) by an error locator polynomial differential value .sigma.'(.alpha..sup.-ju).

Reed-Solomon decoder having a three-stage pipeline structure

There is provided an EFM encoder comprising a DSV calculator which is smaller in circuit scale than a conventional DSV calculator. The above DSV calculator has a merging-bit DSV calculator, a frame-signal DSV/polarity evaluator, adding means, and an overflow/underflow processor. The merging-bit DSV calculator calculates merging-bit DSV data based on merging bits and on a cumulative polarity signal. The frame-signal DSV/polarity evaluator outputs frame-signal DSV data in consideration of the polarity in the final bit of the merging bits. The adding means adds up the cumulative DSV data, the merging-bit DSV data, and the frame-signal DSV data so as to calculate DSV. The overflow/underflow processor performs, when overflow or underflow has occurred in the result of calculation from the adding means, exception handling with respect to the calculation result and outputs the calculation result that has undergone the exception handling as new cumulative DSV data. Even when overflow or underflow has occurred in the obtained cumulative DSV data, the accuracy of DSV calculation performed by the DSV calculator is not reduced.

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Osaka, Japan

Toshihiko Fukuoka