Fujitsu Corporation

Fujitsu Automation Limited

Toshihide Sasaki

Minoru Saitoh

Hiroaki Komatsu

Hiroshi Tsukamoto

Michinori Yajima

The present invention is a simulation apparatus which can shorten the transmission and reception time of events, and unify simulation models to make it possible to use the same language expression as that for an ordinary model to express a real chip. The simulation apparatus comprises a real chip simulation section for carrying out simulation for a portion having an unknown internal logic by using a real chip, a logic simulation hardware section for carrying out simulation for a portion whose internal logic is described, and a high speed dedicated network for transferring event data between the real chip simulation section and the logic simulation hardware section. The simulation apparatus can be applied to hardware accelerators used in logic timing simulation in the field of CAE.

Simulation apparatus

In a logic simulation apparatus formed of dedicated hardware for simulating a logic operation of at least one logic circuit, and connected to at least one host computer, the apparatus includes: a plurality of clusters, each cluster including at least a communication network and a plurality of processor elements connected each other through the communication network; and an upper communication network for connecting among clusters. The host computer is connected to at least one cluster, and the connection configuration among the plurality of clusters is changeable in accordance with the size of the logic operation to be simulated under instructions of configuration change generated by the host computer. The apparatus further includes an error analysis system for the simulation process.

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Shioya-gun, Japan

Toshihide Sasaki