Oki Electric Industry Co., Ltd.

Toshihide Nagatome

Mitsuya Ohie

Kazutoshi Inoue

An input/output buffer circuit is capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to a halt. The input/output buffer circuit has an input/output terminal for performing the input/output of data. When a write enable signal WR is in an active state, the input/output buffer circuit outputs a signal to the input/output terminal. When a read enable signal RD is in an active state, the input/output buffer circuit receives data from the input/output terminal. When the write enable signal WR and the read enable signal RD are both in a non-active state, the input/output buffer circuit outputs a signal based on any of signals supplied thereto.

Input/output buffer circuit

A first supply voltage is applied to a computer-controlled apparatus and to a first block of a simulator, while a second supply voltage is applied to a designator unit and to a second block of the simulator. The operation of the computer-controlled apparatus is simulated by the simulator in response to instruction signals supplied from the designator unit.

Method and system for emulating computer-controlled apparatus

An input circuit is provided with a gate with an input end thereof connected to an input terminal to which an external signal is input, the gate allows or prohibits the output of the external signal in accordance with a control signal. The input circuit also includes a latch circuit that holds the output from the gate and outputs the signal thus held to an internal input terminal. This structure prevents any inflow of a through current, and prevents erroneous operation of an internal circuit resulting from change in the signal level at the internal input terminal.

Input circuit

Disclosed herein is a microcomputer of the present invention. The microcomputer comprises a memory, a peripheral circuit including a circuit whose change of state is fast and which latches data to be held by the circuit therein in response to a data latch signal and outputs the latched data therefrom in response to a first read control signal and a data latch signal generating circuit supplied with the first read control signal so as to generate the data latch signal whose signal time interval is shorter than that of the first read control signal, and a central processing unit which is connected to the memory and the peripheral circuit through a common bus and which outputs an address signal for specifying the circuit and the first read control signal to the common bus to perform access to the circuit and outputs an address signal for specifying the memory and a second read control signal shorter than the first read control signal in signal time width to the common bus to make access to the memory

Microprocessor with common bus for memory and peripheral circuit having

An integrated circuit in which Schmitt input circuits can be tested in a short time and a highly accurate test result can be obtained. The integrated circuit includes switches each passing outputs of Schmitt inverters with inputs connected to input-output ports to the inputs of tristate circuits with outputs connected to adjacent input-output ports. The outputs of the Schmitt inverters may be blocked by the switches from being passed to internal logical circuits. A switch passes the output of the Schmitt inverter to the adjacent tristate circuit during the test of the Schmitt inverter. Alternately, each half of the Schmitt inverters can be tested as predetermined control signals selectively control each switch and each tristate circuit.

Growing community of inventors

Tokyo, Japan

Toshihide Nagatome