Nec Corporation

Nippon Telegraph and Telephone Corporation

Toshiharu Yagi

Shuzo Kato

Shuji Kubota

Convolutional code symbols are sequentially stored into a first buffer at a transmission rate and read therefrom into a decoder where the symbols are decoded at a rate higher than the transmission rate and stored into a second buffer. A controller determines the likelihood of each decoded symbol in accordance with a predetermined likelihood algorithm and causes the decoded symbols to be read out of the second buffer in a backward direction into the decoder when the determination indicates a low likelihood value. When the first buffer is overflowed, the controller causes symbols to be read out of the first buffer into the decoder staring with a symbol which is k symbols older than the most recently received symbol and causes the decoder to shift its symbol timing by one clock interval, where k is an integer ranging from zero to a predetermined number which is smaller than the maximum number of symbols that can be stored in the first buffer.

Sequential decoder having short synchronization recovery time

In a digital receiver, convolutionally coded symbol bits are recovered from a received orthogonally modulated signal. The symbol bits are sequentially stored into a memory and each stored symbol bit is read from the memory as specified by a decoding point address into a sequential decoder, which uses a clock pulse as a boundary point of a codeword. If an overflow condition is detected in the memory, the decoding point address is advanced by K bits. If the overflow still exists, it is repeatedly advanced further by K bits. If the overflow is still detected, then the codeword boundary point is shifted by a clock interval. If the overflow continues, the boundary point shifting is repeated. If the boundary point shifting fails to alleviate the problem, then the decoding point address is advanced to a most recent symbol bit and the recovered symbol bits are phase-shifted by 90 degrees. If a suboverflow condition is detected, the decoding point address is advanced to a most recent symbol bit, and the boundary point shifting is again performed and repeated if the suboverflow still exists. If the suboverflow condition still exists after the boundary point shifting is repeated, the decoding point address is again advanced to a most recent symbol bit and the phase timing shift and the codeword boundary point shift are repeated again.

Quick resynchronization receiver for sequential decoding of

A serial-parallel converter is arranged to convert an information sequence into a plurality of bit sequences. Two convolutional encoders are provided which respectively receive bit sequences from the serial-parallel converter. Each of the two convolutional encoders outputs first and second bit sequences. First parallel-serial converter receives the first bit sequences and converts them into third bit sequence, while second parallel-serial converter receives the second bit sequences and converts them into fourth bit sequence. The third and fourth bit sequences are used to modulate two carriers with a phase difference of .pi./2 radians.

Error control coding arrangement for digital communications system

A decoder is capable of decoding on a maximum likelihood basis coded symbols of requivalently high coding rate which are produced by deleting those code bits which are located at particular positions in a time sequence of convolutional symbols of low coding rate. The decoder includes a serial-to-parallel (SP) converter for converting a serial data sequence from a dummy bit inserter into parallel sequences. The frequency division phase of the SP converter is determined by a second timing signal which the dummy bit inserter produces in synchronism with a dummy bit inserted phase. A code synchronization is established, frequency division phase synchronization is automatically established. This eliminates the need for the repetitive trial for frequency division phase synchronization only and thereby reduces a synchronization capture time.

Decoder with reduced synchronization capture time

In a Viterbi decoder for use in producing a decoded signal by correcting and decoding convolutional codes, a majority circuit (46) is connected to a path memory (45). At each of the time slots used for the respective convolutional codes, the majority circuit makes a decision and selects a decoded datum of the decoded signal in response to a majority of information bits which are memorized in the path memory. The Viterbi decoder consists of a read-only memory, which simplifies the circuit, reduces the required number of circuit elements, and makes a lower cost circuit.

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Tokyo, Japan

Toshiharu Yagi