Kabushiki Kaisha Toshiba

Toshiharu Watanabe

Seiichi Aritome

Kazuhiro Shimizu

Koji Sakui

Yoshiaki Asao

Hiroshi Watanabe

Yuji Takeuchi

Seiichi Mori

Kazuhito Narita

Masataka Takebuchi

Kazuaki Isobe

Junichi Miyamoto

Masaki Momodomi

Hiroaki Hazama

Michiharu Matsui

Keniti Imamiya

Naohiro Matsukawa

Akira Sudo

Hidemi Ishiuchi

Kazumi Amemiya

Kinuyo Tanaka

A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.

Semiconductor memory device

A semiconductor memory device includes: plural word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; plural variable resistance elements each having a first terminal connected to either one of the first and third bit lines; plural active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; plural select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and plural contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line.

A semiconductor memory device includes a first memory cell transistor. The first memory cell transistor includes a tunnel insulation film provided on a semiconductor substrate, a floating electrode provided on the tunnel insulation film, an inter-gate insulation film provided on the floating electrode, and a control electrode provided on the inter-gate insulation film. The floating electrode includes a first floating electrode provided on the tunnel insulation film and a second floating electrode provided on one end portion of the first floating electrode, the floating electrode having an L-shaped cross section in a wiring direction of the control electrode.

Semiconductor memory device and method of fabrication of the same

A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a switching element having a current path with one end and the other end, between which the variable resistor element is connected, the plurality of memory cells having current paths thereof being connected in series, the memory cell array further including a first select element connected to one end of a current path of the memory cell string, and a second select element connected to the other end of the current path of the memory cell string, a bit line which is electrically connected to one end of a current path of the first select element, and a source line which is electrically connected to one end of a current path of the second select element.

Nonvolatile semiconductor memory device and data erase/write method thereof

A trench regionis formed in a memory cell P-type well. Two NAND-type memory cell units NDand NDare respectively formed along both side wall portions of this trench regionA floating gate FG and a control gate CG in these NAND-type memory cell units NDand NDare formed self-aligningly without using memory cell units NDand NDis formed via an interlayer dielectric. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

Nonvolatile semiconductor memory and method of manufacturing the same

A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.

Semiconductor device having MISFETs

A nonvolatile semiconductor memory includes rewritable nonvolatile memory cell transistors connected in series. The nonvolatile memory cell transistors includes at least two charge storage layers formed on a first insulating film, a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, and a second insulating film formed between the at least two charge storage layers and the control gate. A top of the control gate has a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, and the flat surface extends from one of the at least two charge storage layers to the other of the at least two charge storage layers.

Nonvolatile semiconductor memory having control gate with top flat surface covering storage layers of two adjacent transistors

A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Non-volatile semiconductor memory device and method of manufacturing the same

A trench region is formed in a memory cell P-type well. Two NAND-type memory cell units are respectively formed along both side wall portions of this trench region. A floating gate and a control gate in these NAND-type memory cell units are formed self-aligningly without using a photoresist. One bit line connected to the two NAND-type memory cell units is formed via an interlayer dielectric. The bit line pitch of this bit line is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

A non-volatile semiconductor memory device comprising a device isolation insulation layer, a floating gate, and control gate, and a booster electrode. The device isolation insulation layer is formed on a semiconductor substrate, and is for defining a device region. The floating gate is formed above the device region and has a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side. The control gate is formed above the floating gate. The booster electrode has faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer. Dimensions of the floating gate are determined based on a coupling ratio between the floating gate and the booster electrode.

A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

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Yokohama, Japan

Toshiharu Watanabe