Fujitsu Corporation

Fujitsu Microelectronics Limited

Toshiharu Takaramoto

Kunihiko Gotoh

Atsushi Okamoto

There is provided a reference voltage generating circuit including: a first PN junction element (PN) whose forward voltage is a first voltage V; a second PN junction element (PN) having a current density different from the first PN junction element and whose forward voltage is a second voltage Vhigher than the first voltage V; and generating circuits (to) inputting the first voltage Vand the second voltage Vand generating a reference voltage expressed by A&#xd7;V+A&#xd7;(A&#xd7;V&#x2212;A&#xd7;V) in which A, A, and Aare set to be coefficients, and in which Aand Aare different values.

Reference voltage generating circuit

A semiconductor device has transistors (P,P,P) formed in an active region () isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P,P) that require symmetry or relativity characteristics, wherein the distances (S) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.

Semiconductor device comprising transistor pair isolated by trench isolation

The capacitor comprises a lower layer electrode formed on a substrate with an inter-layer insulation film therebetween; an upper layer electrode opposed to the lower layer electrode with an inter-layer insulation film therebetween, a lower interconnection layer formed between the substrate and the lower layer electrode , and electrically connected to the upper layer electrode , whereby the parasitic capacitance, which is a cause for lower capacitor accuracy, useless power consumption, etc. can be drastically decreased, and external noises can be shielded off.

Growing community of inventors

Kawasaki, Japan

Toshiharu Takaramoto