Fujitsu Corporation

Toshiharu Ohshima

Tatsumi Nakada

Akihiro Yoshitake

Eiji Tobita

Yoshiaki Saka

Toshihiro Sakai

Akinao Tanikawa

Tetsuya Ohmura

Yasunori Nozue

A pipeline computer having functions of scoreboard control includes a dependency detection unit provided in the scoreboard for detecting dependency of data between a preceding instruction and a following instruction, the preceding instruction being an instruction which executes prior to the following instruction; and an ensuring unit for the dependency of data detected by the detection unit based on an interlock operation at pipeline processes when an interruption occurs. An interruption instruction waits for completion of an instruction which already starts to execute prior to the interruption instruction, and all register bits on the scoreboard indicating the in use state are reset to the not used state to ensure the dependency of data.

Pipeline computer with a scoreboard control circuit to prevent

The present invention relates to a data processing device that can perform independently a debug interruption process and a program interruption process. The data processing device consists of first and second interruption selection code producing units for producing interruption selection codes according to the first and second interruption requests respectively; and a switching unit for selectively switching to either one of interruption selection codes from said first and second interruption selection code producing units. When the second interruption request is received, the switching unit selects preferentially and output an interruption selection code from the second interruption selection code producing unit, thus jumping to an interruption process program according to the interruption selection code so that an interruption process according to said second interruption request is performed. The data processing device is applicable to RISC-type central processing units in computing systems.

Interrupt control handler for a RISC-type microprocessor

A branch instruction executing device, for sequentially executing instructions in a pipeline process, a) decodes a conditional branch instruction, b) provides a debug exceptional producing flag for indicating the existence of the execution of the debug routine by assuming the success of the condition without waiting for the result of the determination of the condition and c) corrects a content of the debug exception producing flag when the result of the actual determination is later obtained. The execution of the debug routine is canceled when the branch condition is later found not to be successful.

Branch instruction executing device for tracing branch instruments based

There are provided a means for storing an instruction, a first control means for decoding and executing the instruction of said means for storing during a timing period which is used in said instruction, a means for computing an address data required for execution of said instruction, a first storage means having a plurality of registers for storing said computed address data, a means for selecting specific number resister in the first storage means, by controlling of the first control means during a timing period which is not used in said instruction, a second storage means for storing temporarily said address data in the specific number register selected by said means for selecting, a second control means for decoding the instruction before the first control means decoding and finding out the instruction to be branch instruction, and a means for outputting the address data from the second storage means as a target address data, when the register of the first storage means designated by said branch instruction coincides with the specific number register selected by the means for selecting.

Data processor and method of controlling the same

Instruction buffer device for processing an instruction set of

A data processor decoding and executing a train of instructions of variable length. The data processor includes a first instruction control means for temporarily storing a prefetched instruction code and sequentially outputting said instruction code with units of a predetermined number of bits, and a second instruction control means for decoding an instruction code fed from the first instruction control means, generating control information for data processing based on the decoding, and outputting data indicating instruction update demand quantity to the first instruction control means. Based on the data indicating the update demand quantity, the first instruction control means judges whether it has output a valid instruction code of length exceeding the update demand quantity, and provides an indication of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement. As a result, it becomes possible to reduce time necessary for the supply of instruction codes and thus improve a data processing speed as the entire processor.

Data processor decoding and executing a train of instructions of

A microinstruction memory stores microinstructions, and a microinstruction execution unit executes a selected one of the microinstructions by a pipeline process and outputs an operation result. The microinstructions include a specific microinstruction. The data processing apparatus also includes a correction part which has the microinstruction execution unit execute the specific microinstruction when a predetermined event occurs so that the parameter is changed to a corrected parameter which corresponds to a parameter used in an immediately previous pipeline process. The microinstruction execution unit stops operating when the predetermined event occurs and starts the operation again by using the corrected parameter.

Data processing apparatus including a register storing a parameter and a

A first instruction bit string following a memory position indicated as a start point by a read pointer is previously read out from a plurality of memory cells to a plurality of bit lines, a second instruction bit string already transferred to an instruction decoder is temporarily stored in a latch circuit by an instruction length notification signal output from said instruction decoder, and a select circuit selects a next instruction bit string sequentially continuing from a next instruction, between the first and second instruction bit strings without requiring other bit lines or word lines. Therefore, a high speed instruction processing in the pipeline processing can be obtained with a minimum number of transistors and associated wiring required for memory cells in an instruction buffer memory. Large scale integration, small size, and a low cost can therefore be realized.

Data processing device for variable word length instruction system

Microprocessor having a variable length instruction format

A microprocessor provides a CPU to execute a program and a register to store a program status word indicative of a status of the program being executed by the CPU. The program status word includes ring information on the program being executed. A store buffer is provided with write data to be written into an external memory and a corresponding address when the CPU executes a write instruction. The store buffer has a specific area in which ring information on the write instruction is stored. A control part reads out the write data and address from the store buffer and writes the same into the external memory independent of execution of the program by the CPU.

System for transferring first and second ring information from program

A direct memory access (DMA) controlled system which performs DMA data transfer between a main memory, a cache memory, and disk memories while exchanging DMA transfer requests and acknowledgements among disk control units, a memory-to-memory transfer control unit, and a common DMA control unit. The data transfer speed between the main memory and the cache memory is variable according to the load condition of the DMA control unit for the disk memories, enabling the transfer capability of the DMA control unit to be kept at a continually high level.

Direct memory access controlled system

A data processing device having a buffer for prefetching a plurality of instructions. The buffer is constructed by including two switching areas and one common area connecting to one of the two switching areas. An unconnected switching area of the two switching areas is used exclusively for prefetching a destination instruction of a conditional jump instruction, so that the destination instruction is prefetched to the unconnected switching area by a switching operation. Thus flexibility is increased, when the jump instructions are continued. Further, a number of prefetching destination instructions is determined so that a bottleneck in an instruction process is avoided, and thus the capacity of the two switching areas is reduced the hardware scale is not enlarged.

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Kawasaki, Japan

Toshiharu Ohshima