Sharp Kabushiki Kaisha Corporation

Toshiharu Hanaoka

Hiroyuki Furukawa

Masafumi Ueno

Yasuhiro Yoshida

Kenichiroh Yamamoto

Takeshi Hashimoto

Takashi Yoshii

Hiroaki Yabe

In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portionfor converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portionfor superposing an OSD signal on the input image signal, and a controlling portion. The FRC portionhas a motion vector detecting portionfor detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portionfor allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portionfor generating an interpolation frame from the interpolation vector. When the OSD signal is superposed on the input image signal, the controlling portiondisables the motion compensation process of the FRC portionby making the motion vector detected by the motion vector detecting portion0 vector.

Image display device and method

In an image displaying apparatus including a motion compensated rate converting (FRC) portion, deterioration of image quality is prevented in an image having a high-speed region and a low-speed region mixed. The FRC portion includes a motion vector detecting portionand an interpolation frame generating portion. The motion vector detecting portionincludes a first region detecting meansthat detects a first region (high-speed region) including a motion amount equal to or greater than a first predetermined amount from an input image signal, a second region detecting meansthat detects a second region (low-speed region) including a motion amount equal to or less than a second predetermined amount from the input image signal, and a third region detecting meansthat detects a still region from an inter-frame difference of the input image signal. The interpolation frame generating portionexecutes a motion compensated interpolation process using motion vectors for the still region in the first region (background) and executes a zero-vector interpolation process for the still region in the second region (foreground).

Image displaying apparatus and method, and image processing apparatus and method

A three-dimensional image rendering portion, based on image data, performs geometric transformation, projection transformation, etc. and further applies texture data from the texture memory onto polygons, to thereby generate graphic data of a 3-D image. This graphic data is used as pixel data for a frame of image and written into the frame memory. A 3-D texture modeling value generating circuit performs arithmetic operations on 3-D texture modeling values of asperities of the textures, using coordinate data given from the 3-D image rendering portion, bump data stored in the texture memory and parameters stored in the register. These 3-D texture modeling values are provided to 3-D texture modeling circuit where, based on these values, the data from the frame memory is formed into a 3-dimensional form, which in turn is displayed on the display unit.

3-D texture mapping processor and 3-D image rendering system using the

This texture pattern memory circuit is composed of a multi-texture pattern memory, a writing device and a texel selector. The multi-texture pattern memory includes an adder, a subtracter, selectors, 1st to 4th address converting devices, and 1st to 4th memory modules. The texel selector selects only the necessary data from the texel data outputted from the multi-texture pattern memory.

Texture pattern memory circuit for providing plural texel data in

A three dimensional sprite rendering apparatus for producing three dimensional graphic images includes a three dimensional graphic circuit for producing backgrounds of three dimensional graphics and outputting pixel data for each pixel of the backgrounds, and a first buffer storing depth data for each pixel of the backgrounds. The apparatus further includes a voxel character control register for storing control data for voxel characters, a voxel character memory storing geometric data for voxel characters, a volume rendering circuit connected to the voxel character control register and the voxel character memory for producing graphics of voxel characters and outputting pixel data for each pixel of the voxel characters, and a second buffer storing depth data for each pixel of the voxel characters. A depth comparator is connected to the first and second buffers for comparing the depth of a three dimensional background graphic with the depth of a voxel character graphic and generating a control signal according to a result of comparison. An image generation circuit receives the pixel data of backgrounds and the pixel data of voxel characters as well as the control signal, and synthesizes two pixel data inputs according to the control signal.

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Chiba, Japan

Toshiharu Hanaoka