Nec Electronics Corporation

Renesas Electronics Corporation

Canon Kabushiki Kaisha

Toshifumi Takahashi

Hiroshi Furuta

Satoshi Yamamoto

Hideyuki Nakamura

Hidetaka Natsume

Muneaki Matsushige

Isamu Okuma

Masaichi Sato

Hiroyuki Satake

Ryuichi Okamura

Takaaki Kobayashi

Hirofumi Azuhata

Tomoya Morita

A strain wave gear apparatus includes a rigid internal gear, a flexible external gear, and a wave generator. The wave generator includes an input shaft fixing member including eccentric cams, bearings respectively fixed to outer sides of the eccentric cams, and housings respectively fitted to outer peripheral surfaces of the bearings. The eccentric cams are arranged side by side in a direction of an inclined axis inclined with respect to an input rotation axis at an inclination angle (&#x3b8;) in a manner that respective center axes of the eccentric cams are parallel to the inclined axis and decentered in directions opposite to each other from the inclined axis. The housings are each formed into a tapered shape so that an outer peripheral surface of each of the housings is held in surface contact with an inner peripheral surface of the flexible external gear.

Strain wave gear apparatus

In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern regionarranged between the functional circuit regions and between the memory macro regionand the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.

Semiconductor integrated circuit device

A semiconductor device according to an embodiment of the present invention includes: a first region having patterns formed based on grid points as intersections of grid lines; and a second region including a plurality of layout cells an outer edge of which is defined by the grid points, the layout cells having patterns formed based on a wiring rule with patterns connected to patterns of the first region among the patterns being formed based on the grid points at a boundary with the first region.

Semiconductor device and method of designing the semiconductor device

In a semiconductor device including multiple unit cells arranged in an array, transistors are affected by a stress from an STI at different degrees depending on the position in the array. As a result, a variation occurs in transistor characteristic. In a semiconductor device according to the present invention, each of predetermined transistors in outermost unit blocks in the array has a transistor size according to the stress from the STI.

Semiconductor device

A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.

Manufacturing method of semiconductor device having trench isolation

A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

Semiconductor integrated circuit

A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Semiconductor memory device with plural source/drain regions

A memory cell has a first switching element, a second switching element and a storage capacitor and formed in an active region. A first bit line and a first word line are connected to the first switching element and a second bit line and a second word line are connected to the second switching element. A plurality of the memory cells are formed within the active region which extends in a straight line. The active region extends at an angle with respect to the bit and word lines. The active region thus has no bent portions. The deterioration of the characteristics of the memory cell caused by the bent portions can be prevented.

Growing community of inventors

Kanagawa, Japan

Toshifumi Takahashi