Fujitsu Corporation

Toshiaki Usui

Takashi Kawabata

Takehiko Fujiyama

Yuichi Terui

Ryoichi Dangi

Ryouichi Dangi

A phase-locked loop circuit generates a clock signal synchronized with a color burst signal contained in a composite color picture signal. The phase-locked loop circuit contains a phase synchronization loop having a loop gain, extracts the color burst signal from the composite color picture signal, compares the phases of the generated clock signal and the color burst signal, and controls the phase of the generated clock signal to reduce the difference between the above phases. The phase-locked loop circuit further detects the vertical blanking signal, and reduces the loop gain for the duration of the vertical blanking signal. Alternatively, a horizontal synchronizing signal is used instead of the color burst signal. Another phase-locked loop circuit generates a clock signal synchronized with a reference clock signal based on first frequency information indicating a frequency of the reference clock signal. This phase-locked loop circuit generates the clock signal so that the phase of the generated clock signal is controlled according to an output of an amplifier. Second frequency information indicating the frequency of the generated clock signal is generated, and a difference between the frequencies of the reference clock signal and the generated clock signal is obtained. The amplifier amplifies the difference with a gain which can be controlled externally. When a change in the polarity of the difference, a large amount of the absolute value of the difference, or a loss of the first information, is detected, the gain is reduced or suppressed.

Phase-locked loop circuit for generating stable clock signal for use in

In a multipoint videoconferencing system including a plurality of visual telephone terminals and a multipoint control unit (MCU) connected thereto, shares of the respective visual telephone terminals are determined in the MCU, based on determination of a speaker determined from voice levels and/or amount of movement in the respective visual telephone terminals. The respective telephone terminals generate pictures at picture rates defined by the respective shares, and generate video data from the pictures at data rates defined by the respective shares. Video data generated in each visual telephone terminal are multiplexed in time division multiplexer in the MCU, and are distributed to the other terminals.

Adaptively controlled multipoint videoconferencing system

Video and audio multiplex transmission system

A data packing circuit, used in a variable length coder, for receiving code words including variable length codes and code length information of the variable length codes, and packing the variable length codes with no gaps into successive units of bits having predetermined length. The code word is shifted in a first direction by a number of bits equal to a shift number, and in parallel, the code word is shifted in a second direction opposite to the first direction by a number of bits equal to the difference between the predetermined length and the shift number, and zero is filled in each vacant bit which is generated by the above shift operations. The shift number is determined by accumulation of the code lengths by modulo-n addition, n being equal to the predetermined number, and a carry addition of the code lengths whether or not a carry occurs over the above predetermined length in the accumulated value. Logical sums of respective bits of the shifted result in the first direction and corresponding bits of the output of an intermediate date register are obtained. The intermediate data register latches the logical sums in every cycle of the code word when a carry is not detected in the above accumulation, and latches the shifted result in the second direction in every cycle of the code word when the carry is detected. The logical sums are latched as output data of the data packing circuit when the carry occurs.

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Kawasaki, Japan

Toshiaki Usui