Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toshiaki Tsuji

Atsuhisa Kageyama

Kiyoshi Imai

Masazumi Yamada

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Yoshiki Kuno

Hiroyuki Morishita

Makoto Hirai

Ryogo Yanagisawa

Kosuke Yoshioka

Hirotoshi Uehara

Ryuji Matsuura

Shoichi Gotoh

Hironori Akamatsu

Hiroyuki Iitsuka

Toshiroh Nishio

Hisakazu Kotani

Kazuyoshi Nishi

Atsushi Ishizu

Hiroki Monta

Toshihiro Miyoshi

Hideki Ishii

Minoru Miyata

Akifumi Yamana

Naoki Kurita

Hiroyuki Iltsuka

Hiroyuki Oka

Taku Takada

Kazuhiro Takasao

Seiichi Taguchi

A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising:

Multichannel display data generating apparatus, medium, and informational set

A multichannel display data generating apparatus displays AV data on a plurality of screens. A channel displayed on one of the screens is displayed without a program clock reference.

Display apparatus displaying certain data without a program clock reference

The multichannel video processing unit of the invention includes: a decoding section for sequentially selecting a bit stream from a plurality of bit streams each including encoded data of an image of one channel, decoding the selected bit stream by one frame each, and outputting decoded data; a vertical filtering section for sequentially selecting a channel from a plurality of channels corresponding to the decoded images, performing vertical processing for the decoded data corresponding to the selected channel, and outputting vertically-processed data; a horizontal filtering section for sequentially selecting a channel according to the position at which the image is to be displayed, performing horizontal processing for the vertically-processed data corresponding to the selected channel, and outputting horizontally-processed data; and an output processing section for generating a video signal for display of images of a plurality of channels by synthesizing the horizontally-processed data and outputting the generated signal.

Multichannel video processing unit and method

A digital broadcast transmission/reception system includes a transmission posting apparatus for performing a communication call through a telephone line network before a broadcast transmission apparatus starts transmitting individual information. The system also includes a distributor having a register which stores a transmitter ID signal of the transmission posting apparatus. The distributor compares a transmitter ID signal at the communication call with the transmitter ID signal stored in the register, outputs a power control signal when these ID signals match, and connects the telephone line network with a telephone when these ID signals do not match. The system also includes a power control apparatus for tuning ON power to a broadcast reception apparatus according to the power control signal. Therefore, the power to the broadcast reception apparatus can be controlled through the telephone line network.

Power control apparatus, digital broadcast reception system, transmission posting apparatus, power state identification apparatus, communication cutoff decision apparatus, state posting apparatus, state recognition apparatus, state recognition system, and digital broadcast transmission/reception system using them

A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit for decoding compressed video data to produce frame data, frame memory for storing the frame data, a filtering unit for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory for storing the reduced image outputted from filtering unit , and a control unit for controlling filtering unit based on a decoding state of the video data by decoding unit and a filtering state of the frame data by filtering unit , so that overrun and underrun do not occur in filtering unit

Pixel calculating device

A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group , and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

When an STB is powered off when it is not used (when it is changed to the sleep mode) for the purpose of power-saving, a difference in a subtracter immediately therebefore is held by a control circuit and an oscillation circuit is controlled on the basis of the difference, thereby performing reserved processing at a correct time even when the STB is in the sleep mode.

Clock generating based on a reference signal included in the digital input data of a digital broadcasting receiver

A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.

Television receiver for receiving multi-standards

A semiconductor memory device according to the present invention includes a plurality of blocks. A plurality of first selection signals, second selection signals, and third selection signals are provided to the blocks. Each block includes: a memory cell array; a read/write circuit for simultaneously reading out a plurality of data from the memory cell array and subsequently simultaneously writing a plurality of further data into the memory cell array when the corresponding first selection signal is active; a parallel/serial conversion circuit for outputting the plurality of simultaneously read out data, the outputting being performed data by data in a serial manner along the time axis; a transfer gate for a reading operation controlled by the corresponding second selection signal, the gate outputting the plurality of data from the parallel/serial conversion circuit when the corresponding second selection signal is active; a serial/parallel conversion circuit for receiving the plurality of further data, the further data being sequential, and for outputting the plurality of sequential data to the read/write circuit in a parallel manner along the time axis; and a transfer gate for a writing operation controlled by the corresponding third selection signal, the gate outputting the plurality of sequential data to the serial/parallel conversion circuit when the corresponding third selection signal is active. Only one second selection signal is allowed to be active at a given time, while the other remain non-active. Only one third selection signal is allowed to be active at a given time, while the other remain non-active.

Semiconductor memory device having a plurality of blocks each including

A novel video signal correction system is disclosed, in which an average picture level detection circuit detects the average picture level (APL) of a luminance signal, and a coefficient calculation circuit calculates the amount of correction by the APL circuit. An adder adds an APL-corrected signal to a corrected luminance signal. A limiter circuit, on the other hand, limits the lower limit level of an input luminance signal. A divider circuit divides an output signal of the adder by an output signal of the limiter circuit, and the result is used to correct an input color signal. The color signal is thus capable of being corrected in accordance with the APL while at the same time preventing excessive correction of the color signal with a low brightness input.

Video signal correction system

An I-axis phase pulse is allowed to be detected at the sampling point of a chrominance signal with a digitally-implemented circuit. A chrominance signal (sampling frequency f.sub.1) is subsampled by a frequency f.sub.2 (f.sub.1 /N) and subsampling pulses generated in N subsampling pulse generators 10 for N phases, the adjacent ones of the pulses being shifted by one clock (1/f.sub.1) with respect to one another. The subsampled chrominance signal is input to an I-axis determining circuit 17. The I-axis determining circuit operates to detect a maximum value M.sub.1 of a color burst signal (sampling frequency f.sub.1) and the data M.sub.2 after one clock and compare both of the values with each other. Based on the compared result, a selecting signal S.sub.4 is detected for selecting an I-axis phase pulse at the sampling point of the chrominance signal. A selecting circuit 18 selects, as an I-axis phase pulse S.sub.5, a proper one of the N sampling pulse for N phases based on the selecting signal and applies the I-axis phase pulse S.sub.5 to an (N+1)th subsampling circuit 19. The subsampling circuit 19 can provide an I-axis detected output S.sub.3 at the sampling point of the chrominance signal.

I-axis detecting circuit provided in color demodulating circuit of TV

A gradation corrector for use in a television receiver which can subject a signal at any luminance level to non-linear correction to provide optimum image quality. Memory stores therein luminance histogram of an input signal. On the basis of the data, a circuit detects a total frequency, a circuit detects luminance distribution, and a circuit detects the expanse of the luminance distribution. A circuit calculates a fixed value to be added. Further, a circuit detects a minimum luminance level, and a circuit detects an average luminance level. A circuit calculates an accumulation starting point and a circuit calculates an accumulation stopping point. An adder adds the calculated fixed value to the data in the memory. A circuit accumulates the results in the range from the accumulation starting point to the accumulation stopping point. The accumulation result is stored in memory. A circuit detects the maximum cumulative value, and a circuit normalizes all the data stored in the memory by use of this maximum value. The normalized data are stored in a memory. Thus, the input signal is subjected to optimum normalization by use of the normalized data.

Video signal gradation corrector which prevents excessive extension of

A video signal gradation corrector used in a television receiver or the like for preventing the destruction of the gradation of the black side and the floating of the luminance level of the black side and/or an excessive increase of the luminance level of the white side. The corrector can be realized with a small circuit scale. A histogram operating circuit includes an average luminance level detecting circuit. A constant is subtracted from an output signal of the average luminance level detecting circuit by a subtracter. The result of subtraction is multiplied by a constant by a constant-multiplication circuit. A lower-limit limiter circuit limits an output signal of the constant-multiplication circuit to a signal having a value not smaller than 0. An output signal of the lower-limit limiter circuit is provided as an accumulation start luminance level, thereby enabling a gradation correction in which the floating of the luminance level of the black side and the destruction of the gradation of the black side are prevented.

Video signal gradation corrector

In a video signal gradation corrector used in a television receiver, an output of a look-up table memory is supplied to a constant-multiplication circuit, an output signal of the constant-multiplication circuit and an output signal of a look-up table operating circuit are added by an adder, and the result of addition is set into the look-up table memory. Further, a video scene change detecting circuit is provided between an output terminal of the look-up table operating circuit and a coefficient control terminal of the constant-multiplication circuit, and a coefficient of the constant-multiplication circuit is changed in accordance with a change in video scene. Thereby, a correction is made which is not affected by noises, is stable and smooth, and follows the change in video scene.

Video signal gradation corrector providing smooth correction while

In a gradation corrector used in a television receiver, a clipping circuit is connected to an output of a histogram memory and a clipping level of the clipping circuit is changed in accordance with an output of an S/N detecting circuit. Thereby, when the minimum value is detected, it is possible to prevent a large variation of the value to be detected which may be caused from noises or the like. Also, a circuit for detecting a change in video scene and a recursive filter circuit composed of an adder and a xK circuit (and a two-input/one-output selector circuit are provided on the output side of a clipping circuit and the coefficient value K of the xK circuit (or the selector circuit is controlled in accordance with an output of the video scene change detecting circuit. Thereby, it is possible to make a smooth gradation correction which is not affected by noises or the like (or to make a gradation correction with rapid response which follows a change in video scene.

Growing community of inventors

Kobe, Japan

Toshiaki Tsuji