Renesas Electronics Corporation

Toshiaki Terayama

Makoto Nonaka

Ryoji Ishikawa

In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

LSI design method and LSI design device

A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.

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Kanagawa, Japan

Toshiaki Terayama