Fujitsu Corporation

Toshiaki Saruwatari

Atsushi Fujita

Yoshio Hirose

Hiroyuki Utsumi

Koutarou Tagawa

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Bus control system for integrated circuit device with improved bus access efficiency

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

As a result of comparing an address set in an area setting register and an address shown by address information of an access request signal, if the address set in the area setting register matches the address shown by the address information, a command with auto precharge is outputted to an FCRAM, and if not, an ordinary command is outputted to the FCRAM. Thus, when an area, in which addresses to be accessed are random in many cases, is accessed, the command with auto precharge is outputted to allow the FCRAM to perform a precharge operation automatically, and when an area, in which addresses to be accessed are sequential in many cases, is accessed, the ordinary command is outputted to allow a read operation or a write operation to be performed continuously, whereby data transfer efficiency can be increased.

Control device for semiconductor memory device and method of controlling semiconductor memory device

A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.

Break determining circuit for a debugging support unit in a semiconductor integrated circuit

A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.

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Kawasaki, Japan

Toshiaki Saruwatari