Renesas Electronics Corporation

Nippon Crucible Co., Ltd.

Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Device Engineering Co., Ltd.

Toshiaki Sano

Noriaki Maeda

Masanao Yamaoka

Toshiyuki Mine

Tomoyuki Ishii

Yasuhisa Shimazaki

Masao Morimoto

Shigenobu Komatsu

Yasuyuki Okuma

Shinji Tanaka

Makoto Yabuuchi

Ken Shibata

Shunya Nagata

Kazuo Yano

Yoshisato Yokoyama

Tamio Okada

Norifumi Kameshiro

Takeshi Hashizume

Tomohiro Hatanaka

Michio Matsuura

Hideo Yoshikawa

Yoshikazu Saito

Masato Yoshida

Hiroshi Goda

A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.

Semiconductor device

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Semiconductor storage device

A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.

A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Semiconductor integrated circuit device and system

A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Multi-port memory, semiconductor device, and memory macro-cell capable of performing test in a distributed state

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

Memory macro and semiconductor integrated circuit device

Multi-port memory, semiconductor device, and memory macro-cell

Semiconductor integrated circuit device and system with memory cell array

Semicondutor integrated circuit device and system

Growing community of inventors

Tokyo, Japan

Toshiaki Sano