Hitachi-high-technologies Corporation

Toshiaki Nishida

Hideyuki Kazumi

Masahito Mori

Motohiko Yoshigai

Naoshi Itabashi

Takao Arase

Kazutami Tago

Hitoshi Kobayashi

Takahiro Shimomura

Go Saito

Hiroaki Ishimura

Yoshiharu Inoue

Masunori Ishihara

Toru Ito

The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.

Dry etching method

An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or 'high-k' insulator is provided. To this end, place a workpiece on a lower electrode located within a vacuum processing vessel. The workpiece has a multilayer structure of an electrode material layer which contains therein a transition metal element and a dielectric material layer made of high-k insulator. Then, while introducing a processing gas into the vacuum processing vessel, high-frequency power is applied to inside of the vacuum processing vessel, thereby performing plasma conversion of the introduced processing gas so that the workpiece is etched at its surface. When etching the electrode material layer, an HCl gas is supplied as the processing gas.

Plasma etching method

A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing AlOand a polysilicon or SiOlayer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl, Ar, and CHor He. The gas mixture further contains Cl. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100&#xb0; C. to 200&#xb0; C. The interlayer insulating layer and the polysilicon or SiOlayer are separately etched in different chambers.

Method for manufacturing semiconductor devices

Growing community of inventors

Kudamatsu, Japan

Toshiaki Nishida