Hitachi, Ltd.

Toshiaki Matsubara

Akira Uragami

Masahiro Iwamura

Ikuro Masuda

Yukio Suzuki

Masayoshi Yoshimura

Shinji Kadono

Yasunaga Suzuki

Akira Urragami

Akiro Uragami

Haruo Mamyoda

In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

BiCMOS tri-state output driver

Level conversion circuitry for a semiconductor integrated circuit

In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Disclosed is a semiconductor integrated circuit device equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the input buffer portion, circuit elements for an output circuit disposed at the output buffer portion are used in order to constitute the input protection circuit.

Semiconductor integrated circuit device

A semiconductor integrated circuit device is disclosed. The circuit device uses modified (m+n) input cells, each equipped with high load driving functional elements disposed at the periphery of the cell, and having n signal input terminal(s) in addition to m normal signal input terminals that are incorporated in the cell.

Semiconductor integrated circuit with a bi-MOS input circuit for

Bicmos gate array

A semiconductor integrated circuit device is provided which is equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the input buffer portion, circuit elements for an output circuit disposed at the corresponding output buffer portion are used in order to constitute the input protection circuit.

A semiconductor integrated circuit device is provided which is equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the corresponding input buffer portion, circuit elements for an output circuit disposed at the output buffer portion are used in order to constitute the input protection circuit. Therefore, the circuit elements of the corresponding output buffer portion, which normally would be unused, are utilized to provide an important circuit function.

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Takasaki, Japan

Toshiaki Matsubara