Hitachi, Ltd.

Hitachi Maxell, Limited

Hitachi Vlsi Engineering Corp.

Hitachi, Vlsi Eng. Corp.

Toshiaki Masuhara

Osamu Minato

Yoshio Sakai

Katsuhiro Shimohigashi

Toshio Sasaki

Shoji Hanamura

Masaharu Kubo

Masaaki Aoki

Koichiro Ishibashi

Toshiaki Yamanaka

Satoshi Meguro

Hideo Sunami

Nobuyuki Moriwaki

Shigeru Honjyo

Kazuo Yano

Tokuo Kure

Yoshifumi Kawamoto

Shinji Shimizu

Masanobu Miyao

Minoru Nagata

Mitsumasa Koyanagi

Hajime Akimoto

Masashi Horiguchi

Masakazu Aoki

Yoshinobu Nakagome

Naotaka Hashimoto

Kouki Noguchi

Toru Baji

Shinya Ohba

Norio Koike

Tetsuya Nakagawa

Katsuro Sasaki

Eiji Takeda

Shinichi Ikenaga

Katsuki Miyauchi

Kouichi Nagasawa

Motonobu Tonomura

Norikazu Hashimoto

Tokumasa Yasui

Shigeru Honjiyo

Kiyoo Itoh

Shuji Ikeda

Katsutaka Kimura

Takashi Hashimoto

Iwao Takemoto

Akihiro Shimizu

Jun Etoh

Hideo Nakamura

Isao Yoshida

Mikio Hongo

Yoshiaki Kamigaki

Masao Mitani

Kensuke Ogawa

Yoshimune Hagiwara

Hiroo Masuda

Toshio Katsuyama

Tetsuya Hayashida

Kenji Kaneko

Masatoshi Ohtake

Naoki Ozawa

Ken Yamaguchi

Tateoki Miyauchi

Toshiyuki Usagawa

Tetsuichi Kudo

Hideaki Kato

Hisao Katto

Terunori Warabisako

Hiroshi Kakibayashi

Takashi Nishida

Kenji Hiruma

Yasunobu Kosa

Hidehito Obayashi

Kiyoshi Aiki

Kotaro Nishimura

Takeaki Okabe

Yoshio Uetani

Kazuhiro Kondo

Mineo Katsueda

Nobuo Hamamoto

Kazutoshi Ashikawa

Shigeru Honjo

Shojiro Asai

Kiyotsugu Ueda

Seiichi Isomae

Mitsuo Ito

Shin-ichi Muramatsu

Isamu Orita

Shigeo Ohtaka

Akihiro Tomozawa

Tadashi Onishi

Hiroshi Kishida

Gerard P Morgan

Isao Tanabe

Hisashi Horikoshi

Keiichi Haraguchi

Masamits Yazawa

Joh Nakajima

Fumio Kojima

In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone. The fast and slow playback are possible without deteriorating the sound quality, and ripples can be greatly reduced against the digital input signal, thereby making possible a faithful data compression of an acoustic signal or the like by a simple configuration. The self-diagnosis function permits the use of a defective memory chip, thereby leading to a very economical system.

Digital information system, digital audio signal processor and signal converter

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Apparatus including a pair of neural networks having disparate functions

A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.

Semiconductor optical device with nanowhiskers

A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Semiconductor memory

A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

Semiconductor memory with divided bit load and data bus lines

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Customized personal terminal device

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Semiconductor memory device having flip-flop circuits

Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device). Such low impurity concentration layer is formed by evaporating amorphous silicon on a surface region of a semiconductor region of the device and passing the device through a low-temperature annealing process, the low impurity concentration layer having a lower total impurity concentration than that of the semiconductor region thereunder and having a thickness not more than 100 nm.

Process for making MOS devices for low-temperature operation

In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Homo-junction bipolar transistor having high base concentration and

Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Semiconductor devices and a process for producing the same

In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of '0' and '1', and don't care value 'X'. The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

Semiconductor memory device

A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.

Growing community of inventors

Tokyo, Japan

Toshiaki Masuhara