International Business Machines Corporation

Globalfoundries Inc.

Siemens Aktiengesellschaft

Other

Globalfoundries U.S. Inc.

Kabushiki Kaisha Toshiba

Infineon Technologies Ag

Infineon Technologies North America Corp.

Toshiaki Kirihata

Gerhard Mueller

Subramanian Srikanteswara Iyer

Gregory J Fredeman

Louis L Hsu

Hing Wong

Sami Rosenblatt

David R Hanson

Srivatsan Chellappa

Balaji Jayaraman

Sang Hoo Dhong

Hoki Kim

Ramesh Raghavan

Chorng-Lii Hwang

Derek H Leu

Matthew R Wordeman

Brian L Ji

Rajesh Reddy Tummuru

Darren Lane Anand

John Matthew Safran

John W Golz

Dmitry G Netis

Yohji Watanabe

Thejas Kempanna

L Brian Ji

Rajiv V Joshi

John Kenneth DeBrosse

Chandrasekhar Narayan

Mark David Jacunski

Gabriel Daniel

Janakiraman Viraraghavan

Alan James Leslie

Alper Buyuktosunoglu

Arvind Kumar

Chandrasekharan Kothandaraman

Wei Hwang

Li-Kong Wang

Paul Christian Parries

Seiji Munetoh

Wing Kin Luk

Dan Moy

Krishnan Santhana Rengarajan

Dale E Pontius

Troy Lawrence Graves-Abe

Daniel George Berger

Karthik V Swaminathan

Norman Whitelaw Robson

Daniel W Storaska

Winfried W Wilcke

Karl-Peter Pfefferl

Deepal Wehella-Gamage

Paul William Coteus

Chengwen Pei

Louis Lu-Chen Hsu

John Edward Barth, Jr

Gregory John Uhlmann

Toshio Sunaga

Edward P Maciejewski

Hyun J Shin

Hwa-Joon Oh

Steven William Tomashot

David F Heidel

Jean-Marc Dortu

Daniel Jacob Fainstein

Pooja R Batra

Jeffrey P Gambino

Claude Louis Bertin

William R Tonti

Warren Edward Maule

John Atkinson Fifield

Robert H Dennard

Robert C Wong

William Paul Hovis

Phil Christopher Paone

Yoichi Taira

William Robert Reohr

Anthony Gus Aipperspach

Donald W Plass

Yasunao Katayama

Kevin William Gorman

Gerd Frankowsky

Heinz Hoenigschmid

Xiaojun Yu

Anda C Mocuta

Jeremy K Stephens

William Wu Shen

Axel Christoph Brintzinger

Lewis M Terman

Munehiro Yoshida

Kenneth C Arndt

Phil Christopher Felice Paone

David Edward Schmitt

Somnuk Ratanaphanyarat

Alan D Norris

Jonathan R Fales

Koji Kitamura

John E Barth

John M Ross

Jay M Shah

Chandrahasa Reddy Dinnipati

The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (OTPM)

Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.

Memory with read circuit for current-to-voltage slope characteristic-based sensing and method

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Charge trap memory devices

A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

Twin cell memory-based physically unclonable function

Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Authenticating a hardware chip using an intrinsic chip identifier

The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

Data dependent sense amplifier with symmetric margining

The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

Program and erase memory structures

Providing an authenticating service of a chip

A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

Double-sided segmented line architecture in 3D integration

Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

Test method and structure for integrated circuits before complete metalization

Growing community of inventors

Poughkeepsie, NY, United States of America

Toshiaki Kirihata