Fujitsu Corporation

Toshiaki Kinoshita

Shigeo Tani

Shosaku Yamasaki

Katsuaki Yamanaka

Hironori Aono

Kunio Aduma

In an SDH transmission apparatus, an intra-apparatus reference frame timing produced by a main signal processing unit (A/B) which accommodates a plurality of interface units () is distributed to the interface units () by a frame timing production section (-) to suppress displacements of the frame top positions of the main signals from the IF boards to the minimum, whereby frame timing re-clocking of the main signals is performed with the least necessary memory capacity without using a pointer processing technique so that, even if the number of channels to be processed increases, the apparatus scale can be suppressed to the minimum.

SDH transmission apparatus and frame timing re-clocking method for SDH transmission apparatus

The oscillator with cycle time correction includes a low accuracy oscillator A generating a clock CLK , a counter counting the clock CLK and cleared by activation of a clear signal CLR , a register storing a count CN of the counter as a reference value RV in response to activation of a capture signal CAP; a comparator activating a coincidence signal EQ when CN&equals;RV, a control register including a bit outputting a clear signal CLR , a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits and activating the clear signal CLR when the clear signal CLR is active or when the enable signal EN and the coincidence signal EQ are both active.

Divider with cycle time correction

A digital communication system includes a first station, a second station and a network therebetween. The first station includes a clock selecting device for selecting one clock from a plurality of different clocks; and a transmitting device for transmitting frames to the second station based on the selected clock. The second station includes an evaluating device for evaluating transmission quality of data in each of the frames received from the first station; and a quality message inserting device for inserting the evaluated transmission quality as a quality message into a part of the corresponding frame to be transmitted to the first station. The first station further includes a message processing device for extracting the quality message from each received frame to convert the extracted quality message into a corresponding message signal to output the message signal; and a control device for causing the clock selecting device to select a clock corresponding to the message signal output from the message processing device.

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Yokohama, Japan

Toshiaki Kinoshita