Nec Corporation

Pioneer Corporation

Sanshin Shokai Co. Ltd.

Nec Compound Semiconductor Devices, Ltd.

Toshiaki Inoue

Toshirou Watanabe

Toshiro C Watanabe

Wataru Onodera

Kiyoshi Chikamatsu

Koji Shibata

Ryohei Kagawa

Yasushi Kose

Yuji Ito

Katsuyuki Hashimoto

A point which requires visual attention is added to map data. A map data generation device acquires image data in which the outside is captured from a vehicle by an input device and a point data of the vehicle, associates both data, and generates a visual saliency map acquired by estimating fluctuation of visual saliency based on the image data by the visual saliency extraction unit. Then, whether or not a point or a section indicated by position information corresponding to the visual saliency map is a point or a section which requires visual attention is analyzed based on the visual saliency map by an analysis unit, and the point or the section which requires the visual attention is added to the map data based on an analysis result of the analysis unit by an addition device.

Map data generation device

A data transfer circuit comprises a voltage/current converter circuit for converting a first binary voltage data of n bits (n is an integer equal to or larger than two) to multi-value current data of 2values which is output to a single data transfer line. A current comparator circuit converts the multi-value current data on the data transfer line to binary current data of (2&#x2212;1) bits, and a current/voltage converter circuit converts the binary current data of the (2&#x2212;1) bits to second binary voltage data of (2&#x2212;1) bits. A counter circuit restores the first binary voltage data of the n bits from the second binary voltage data of the (2&#x2212;1) bits.

Data transfer method, data transfer circuit, output circuit, input circuit, semiconductor device, and electronic apparatus

A method for accessing a frame memory integrated within a display panel driver driving a display panel is composed of serially performing write operations for writing sub-field data of a pixel line within the display panel for a plurality of sub-fields into the frame memory, and serially performing read operations for reading sub-field data of a plurality of pixel lines for a sub-field from the frame memory. At least two of the write operations are allowed to be performed between adjacent two of the read operations.

Method and device for accessing frame memory within display panel driver

A low-cost digital image processing device constructed by using a simplified circuit is provided which is capable of reducing an amount of data of an image to be stored in a frame memory and of being applied to a display panel with a desired level of a resolution. In the digital image processing device, a video input signal is processed in a signal processing unit and is stored in a frame memory as image data. The frame memory is installed to play a role as, for example, a double buffer to smooth out transfer speed discrepancies between a video input signal and a video output signal. Dummy data is embedded in an image data read from the frame memory by a redundant pixel embedding section and the image data is fed to a display panel as a video output signal.

Digital image processing device

In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with &ldquo;0&rdquo;. A Booth decoder divides the multiplier into a plurality of partial bit rows. A plurality of partial product generating circuits, each of which is arranged corresponding to corresponding one of the partial bit rows divided by the Booth decoder, each generates a partial product of a multiplicand and each corresponding one of the partial bit rows. In the case of performing the multiplication operation with low accuracy, the partial product generating circuits generating the partial products corresponding to the partial bit row of the least significant half the bits, generate partial products of each corresponding bit row and the least significant half the bits of the multiplicand, and generate partial products of each corresponding bit row and the most significant half the bits of the multiplicand. The partial products, which are generated by the plurality of partial product generating circuits generate, are added by means of adders which are separately arranged for corresponding to either the most significant half the bits or the least significant half the bits. In the case of performing the multiplication operation with low accuracy, a carry signal which is generated by adding the least significant half the bits of the partial products is not input in the adder being in charge of adding the most significant half the bits.

Multiplier and arithmetic unit for calculating sum of product

A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 &OHgr;. The drain pads are connected to each other by a drain extraction electrode connection wiring line. A method of manufacturing this semiconductor device is also disclosed.

Method of manufacturing a plural unit high frequency transistor

A semiconductor device provided with a field effect transistor having a electrode pads for wire-bonding comprises a first electrode pad for wire-bonding directly connected with the field effect transistor, and a second electrode pad for wire-bonding connected with the field effect transistor via a resistor. According to the semiconductor device, a chip used in the field effect transistor can be used in different frequencies by changing bonding.

Semiconductor device

Plural transistor device with multi-finger structure

Disclosed is a register file used in a multiprocessor composition composed of a plurality of processor elements, the register file having a plurality of words and being provided for each of the plurality of processor elements, wherein: the plurality of words are divided into a word part that can be simultaneously accessed by some of the plurality of processor elements to use in common with other processor element, and a word part that can be accessed only by its own processor element.

Register file having shared and local data word parts

An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the augend signal bits, the addend signal bits and the carry bits supplied from lower-digits, a carry propagation block responsive to control signal bits for dividing the adder into partial adders and having propagation stages for producing carry signal bits from the carry generation signal bits, the carry propagation signal bits and the control signal bits, and a sum generation block for producing sum signal bits from the carry propagation signal bits, the control signal bits and the carry signal bits, and is divisible into an arbitrary number of partial adders without increase the stages of a critical path.

Method of adding two binary numbers and binary adder used therein

A semiconductor device includes: a plurality of first field effect transistors (FETs) having a gate formed on a main surface of a semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; a plurality of second FETs having a gate formed on the main surface of the semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; and an electrically conductive layer that penetrates the main surface and a back surface of the semiconductor substrate in a region between the pair of FETs; wherein the first and second FETs that form the pair of FETs are disposed close to each other so that their drains are opposite to each other; wherein region widths of the first and second FETs in a direction of shorter sides of sources thereof are substantially identical with region widths of the first and second FETs in a direction of shorter sides of drains thereof; wherein all the drains of the first and second FETs are electrically connected to each other; wherein all the gates of the first and second FETs are electrically connected to each other; and wherein all the sources of the first and second FETs are electrically connected to each other on the back surface of the semiconductor substrate through the conductive layer.

An apparatus and a method of positioning pallets on roller chains mounted on a free flow conveyor is basically composed of a detector for detecting an oncoming pallet, a stopper for stopping the pallet at an approximately required position, a controller capable of positioning the pallet in the x- and y-directions, and another controller capable of positioning the pallet in the z-direction. With an application of the foregoing method proposed, a device is designed to provide a highly accurate positioning of the pallet with a single device and therefore contributes greatly to an economization of operating costs.

Method of positioning pallets and device thereof

A free flow conveyor which conveys in order a plurality of pallets freely loaded on roller chains in a required direction comprises a conveying feed path for the pallets to be defined at a first horizontal elevational level, another conveying return path for the pallets to be defined therebelow, and roller chains, to be mounted on both sides of the conveying paths, being endlessly wound in common with both feed and return paths so that the roller chains can be commonly driven. This invention will therefore provide a simple mechanism and a reduction in operating costs so as to eliminate the disadvantages of a free flow conveyor to which the prior art pertains.

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Tokyo, Japan

Toshiaki Inoue