Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Toshiaki Dozaka

Yuki Watanabe

Kenichi Anzou

Tsuyoshi Midorikawa

A determination circuit according to an embodiment includes a first capacitive element that has one end connected to an input terminal of a differential pair included in a differential type determination circuit, and shifts a potential of the input terminal so as to reduce a potential fluctuation of the input terminal that occurs due to start of operation of the differential pair. Therefore, in a clock synchronization latch type determination circuit, a potential fluctuation during operation can be suppressed without increasing an installation area more than necessary, and determination can be performed with high accuracy.

Determination circuit and correction method

According to one embodiment, an integrated circuit includes a first power supply line, a protection circuit, an internal circuit, a second transistor, and a shutoff control circuit. A first power supply voltage is supplied to the first power supply line. The protection circuit is connected to the first power supply line. The internal circuit includes a first transistor whose breakdown voltage is lower than the first power supply voltage. A drain or a source of the first transistor is connected to the first power supply line. The second transistor is on the first power supply line between the protection circuit and the internal circuit and is configured to switch between conduction and non-conduction states to connect and disconnect the protection circuit and the internal circuit from one another along the first power supply line. The shutoff control circuit is configured to turn off the second transistor during an ESD operation.

Integrated circuit with ESD protection

According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.

Storage device

According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.

Semiconductor memory device with write assist control

According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.

Semiconductor device

According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that controls the first circuit, wherein in a sequence in which the second circuit writes first data in the memory cell, the first circuit generates a first current of a first current value, and determines data stored in the memory cell based on the first current and a second current flowing in the memory cell, and in a sequence in which the second circuit writes second data different from the first data in the memory cell, the first circuit generates a third current of a second current value different from the first current value, and determines data stored in the memory cell based on the third current and the second current.

Semiconductor memory device

According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.

Semiconductor memory device and control method of semiconductor memory device

According to one embodiment, a semiconductor integrated circuit includes a logic circuit and a memory macro. The memory macro includes: a memory cell array including a memory bit cell; an output buffer; a sense amplifier configured to output data read from the memory cell array based on a first clock signal; a write driver configured to apply a write voltage; and a first register circuit that configured to fetch first input data based on a second clock signal, output the first input data to the write driver based on the second clock signal in a write operation, and outputs the first input data to the output buffer based on the first clock signal in a scan test of the logic circuit.

Semiconductor integrated circuit

A determination circuit of one embodiment includes first and second inverter circuits, a first transistor which turns on when receiving an asserted first signal, and a first capacity component including a first end which receives an inversion signal of the first signal. The second inverter circuit includes an input coupled to an output of the first inverter circuit, and includes an output coupled to an input of the first inverter circuit. The first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node.

Determination circuit

According to one embodiment, the semiconductor memory device includes a memory element, a reference resistance element, a read circuit, and a first circuit. The memory element is enabled to take a first resistance value and a second resistance value. The reference resistance element configured to have a resistance value between the first resistance value and the second resistance value. The read circuit is configured to determine data read from the memory element based on a current flowing through the memory element and a current flowing through the reference resistance element. The first circuit is configured to suppress the currents flowing through the memory element and the reference resistance element in response to determination of data read from the memory element.

A semiconductor memory device according to an embodiment includes first and second storages that enable writing and reading of data. The first decoding line and the third decoding line are electrically connected to each other. The first bit line and the third bit line are electrically connected to each other.

A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.

Growing community of inventors

Yokohama Kanagawa, Japan

Toshiaki Dozaka