Fujitsu Corporation

Toru Watabe

Yoshio Hirose

Takumi Kishino

Yasutomo Sakurai

Takumi Takeno

Koichi Odahara

Takato Noda

Shinya Katoh

Kazuhiro Nonomura

Kenichi Kobayashi

Hiroshi Murakami

Megumi Yokoi

Kouichi Odahara

Hiroshi Wachi

Yasumasa Honjo

A memory access method is employed in a multiprocessor system which includes a plurality of system modules coupled via a crossbar module, where each of the system modules includes a buffer which holds data and a plurality of processors having a cache memory which temporarily holds data. The memory access method includes a step, responsive to a read request from a processor within an arbitrary system module, holding data preread from a system module other than the arbitrary system module in a buffer within the crossbar module.

Multiprocessor system and memory access method

A multiprocessor system includes a plurality of system modules each having a plurality of processors, a transfer controller and a first crossbar, a crossbar module including a second crossbar, a control bus coupling the transfer controller of each of the system modules to the crossbar module, and a data bus coupling the first crossbar of each of the system modules to the crossbar module. Within an arbitrary one of the system modules, the first crossbar outputs a data packet to the data bus in response to a command signal from the transfer controller after the transfer controller outputs a control information packet to the control bus.

Multiprocessor system with system modules each having processors, and a data transfer method therefor

An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend or restrain issuance of address transactions, other than the excessively retried address transaction, and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of a presence of the excessively retried address transaction by the bus-control unit.

Transaction retry in multi-processor system

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Information processing system

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Kawasaki, Japan

Toru Watabe