Tsubakimoto Chain Company

Panasonic Corporation

Toru Wada

Yoshifumi Takeuchi

Shoichiro Komiya

Masaya Sumita

Masaaki Ikeda

Isao Tanaka

Takayuki Matsuda

Akihiko Utaki

Tomoyuki Saji

Osamu Taketoshi

Masahiro Sudare

Kiyoshi Fukuyama

Naoto Shibata

Kazuya Ohminami

Junichi Kaisaku

Kazunori Nakayama

Kozo Kitabata

Shigemi Tsuchitani

Provided is an interlocking chain-type forward and backward actuating device, the device being configured so that an increase in the number of parts is minimized, an increase in the size of the device is avoided, the amount of scattering of lubricating oil to the outside of the device is reduced, the wear of connection pins is reduced, the breakage of the connection pins is avoided, and the striking noise and vibration of the chains occurring during the reception of the chains are reduced. Chain guide plates are respectively provided on both sides of a pair of interlocking chains in the chain width direction. Chain locus restriction members having chain locus restriction faces in contact with rigid chain portions, which are made rigid by engaging and integrating the pair of interlocking chains with each other, are disposed so as to be adjacent to the rigid chain portions.

Engagement chain type device for operating forward and backward movement

The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN in synchronization with the reference clock CK; a frequency divider circuit for multiplying the frequency of the reference clock CK by n/m (m and n are integers equal to or more than 2 and m&#x3e;n); a data signal buffer circuit for transmitting a data signal held by the transmitter flipflop circuit; and a clock buffer circuit for transmitting the output of the frequency divider circuit.

Semiconductor integrated circuit, communication apparatus, information playback apparatus, image display apparatus, electronic apparatus, electronic control apparatus and mobile apparatus

A combinational circuit is connected to a flip-flop circuit. A clock buffer supplies a clock to the flip-flop circuit. A control circuit controls a delay time of the flip-flop circuit and a delay time of the combinational circuit independently.

Semiconductor integrated circuit

An engagement chain type hoisting and lowering device is disclosed, having a hoisting and lowering table attached to the upper end of two or more pairs of hoisting and lowering driving engagement chains. A driving motor drives two pairs of hoisting and lowering sprockets which, in turn, raise or lower two pairs of hoisting and lowering driving engagement chains. By arranging two pairs of hoisting and lowering driving engagement chains on two opposed sides of the hoisting and lowering table, buckling of the hoisting and lowering driving engagement chains is suppressed, resulting in stable hoisting and lowering operations without slippage of articles on the hoisting and lowering table, and chain endurance is improved. The device is designed so that the lowest position of the hoisting and lowering table can be lower than the height of the peripherally located driving motor, for ease and safety of operation and maintenance.

Hoisting and lowering device having engagement chains

To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.

Processor system, instruction sequence optimization device, and instruction sequence optimization program

To provide a link bodies-connected cable drag chain, in which even in a case where a long flexible body C such as a cable, a hose or the like is incorporated a roller, which protects the flexible body, can be easily detached from the link bodies. The cable drag chain of the present invention is formed by articulately connecting a plurality of link bodies each having a pair of plates . Between the pair of plates is rotatably provided a roller , which protects the flexible body. In the plate is formed a through-hole larger than the outer diameter of the roller , and to this through-hole is detachably fit-secured a plug, which protects the dislodgement of the roller . When this plug is removed the roller can be easily detached from the through-hole

Cable drag chain

A three dimensional sorting apparatus utilizes a plurality of frame members, supported for circulating movement in a closed path. A tray is mounted for up and down movement on each of the frame members and is guided along rails which determine its height. Change-over rails, controlled to move up and down, are provided to connect a first guide rail extending past an intake station to a selected one of a plurality of secondary guide rails extending at different levels past a plurality of discharge stations. This enables an article to be discharged into a selected one of several discharge ports at a selected discharge station. Discharge is carried out by pivoting the tray forward upon release of a tray-retaining latch by a discharge assisting device at each discharge station. Alternatively, the article is carried on a conveyor driven by a pinion which is activated by a discharge assisting rack at each discharge station.

Growing community of inventors

Osaka, Japan

Toru Wada