Fujitsu Corporation

Toru Tsuruta

Yuji Nomura

Norichika Kumamoto

Ritsuko Tanaka

Masayoshi Shimizu

Ryuta Tanaka

Yuushi Toyoda

Nobuyuki Iwasaki

Soutaro Kaneko

Eishi Morimatsu

Hideki Yoshizawa

Teruo Ishihara

An image processing device includes: first to third address registers that store three addresses, respectively, the three addresses indicating three bank regions, respectively; an input image bank managing unit that, when the image processing device receives an image from an imaging device, switches, between the first address register and the second address register, and sets a flag and supplies the address stored in the first address register as an address for writing the received image; an imaging processing unit that performs image processing on the received image; and an image processing bank managing unit that, when the flag is in a set state and the processed image is switched to another image to be processed, switches, between the second address register and the third address register, resets the flag and supplies to the image processing unit the address stored in the third address register.

Image processing device, image processing system and bank management method

An image synthesis apparatus includes an image obtainer obtaining a plurality of images taken by a plurality of cameras; a pixel value corrector which, with respect to each of the images, calculates a correction factor of an average pixel value in overlap regions located at the both ends of an image and, in the adjacent direction of the images, calculates the correction factor of a pixel value in a region other than the overlap regions by a predetermined continuous function connecting the correction factors in the overlap regions and corrects the entire image based on the calculated correction factor; a synthetic image generator synthesizing the images corrected by the pixel value corrector to generate one synthetic image; and an image output outputting the synthetic image to an external apparatus.

Image synthesis apparatus and image synthesis method

An image processing apparatus includes a low-frequency-component storage unit that stores therein a low-frequency component generated from a frame in an input moving image composed of a plurality of frames, a low-frequency-component generating unit that generates a low-frequency component from an N-th frame of the input moving image, and stores the low-frequency component in the low-frequency-component storage unit, and a dynamic-range correcting unit that corrects a dynamic range by using an (N+1)-th or later frame of the input moving image and the low-frequency component of the N-th frame stored in the low-frequency-component storage unit.

Image processing apparatus and image processing method

An image processing apparatus holds a plurality of intermediate smoothed images smoothed at a plurality of preset level values, reduces the N-th frame image of a moving image received from the outside to generate a reduced image, performs a smoothing process on the generated reduced image at the plurality of preset level values to generate a plurality of intermediate smoothed images, stores the generated intermediate smoothed images in an intermediate smoothed image storing unit, acquires, when generating the smoothed images of the frames after the (N+1)-th frame, one or a plurality of intermediate smoothed images from the plurality of intermediate smoothed images of the N-th frame stored in the intermediate smoothed image storing unit, synthesizes the acquired intermediate smoothed images of the N-th frame and the frames after the (N+1)-th frame of the moving image received from the outside, and generates smoothed images.

A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.

System and method for controlling DMA data transfer

The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Multiprocessor system, multiprocessor control method, and multiprocessor control program retaining computer-readable recording medium

A memory controller includes a memory unit having an n-byte memory data width, a register unit consecutively reading out, in response to an enable signal supplied thereto, data from the memory unit having n-byte size, the register unit further recording therein the data read out from the memory unit in the form of continuous data of 2n&minus;1 bytes including the last data read out from the memory unit, a shifter unit selecting consecutively a block of continuous n-byte data from the continuous data of 2n&minus;1 bytes recorded in the register unit, the shifter unit supplying the continuous n-byte data block to an output terminal, and a control unit controlling the memory unit, the register unit and the shifter unit.

Memory controller and an information processing apparatus with improved efficiency

A parallel processor system is constructed to include a pair of parallel buses ( ), pipeline buses ( ), a plurality of processor nodes ( - to -N) having functions of carrying out an operation process in response to an instruction and transferring data, cluster switches ( - to -N, - to -N, - to -La, - to -&plus; - to -Ma, - to -(M&minus;1) ) having a plurality of connection modes and controlling connections of the parallel buses, the pipeline buses and the processor nodes, and a switch controller ( ) controlling the connection mode of the cluster switches and coupling the processor nodes in series and/or in parallel.

Parallel processor system

A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Signal processing device accessible as memory

An information processing apparatus is constructed to include a judging part for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and a control part for carrying out a cache control when the judgement signal from the judging part indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request.

Information processing apparatus and storage medium

A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.

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Kawasaki, Japan

Toru Tsuruta